Freescale Semiconductor HCS08 Series, Reference Manual

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Chapter 5 Resets, Interrupts, and System Configuration
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 73
5.7.4 System Options Register 1 (SOPT1)
This register may be read at any time. Bits 4 and 3 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT
must be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
Table 5-4. SBDFR Register Field Descriptions
Field Description
0
BDFR
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This
bit cannot be written from a user program.
R
COPT STOPE
1 0 BLMSS
BKGDPE RSTPE
W
Reset: 1 1 0 1 0 0 1 u
(1)
POR: 1 1 0 1 0 0 or 1
(2)
1 0
LVR: 1 1 0 1 0 0 1 u
1
u = unaffected
2
Depends on PTB3/BLMS pin state.
Figure 5-5. System Options Register (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Field Description
7:6
COPT[1:0]
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See Table 5-6 .
5
STOPE
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
2
BLMSS
BLMS Pin State — This read only bit indicates PTB3/BLMS pin state during power-on reset (POR).
0 BLMS pin is high during POR
.
1 BLMS pin is low and MS pin is high during POR.