Freescale Semiconductor HCS08 Series, Reference Manual

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16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
196 Freescale Semiconductor
13.3.3 SPI Baud Rate Register (SPIBR)
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
Normal 0 X Master In Master Out
Bidirectional 1 0 MISO not used by SPI Master In
1 Master I/O
Slave Mode of Operation
Normal 0 X Slave Out SlaveIn
Bidirectional 1 0 Slave In MOSI not used by SPI
1 Slave I/O
7 6 5 4 3 2 1 0
R 0
SPPR2 SPPR1 SPPR0
0
SPR2 SPR1 SPR0
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 13-7. SPI Baud Rate Register (SPIBR)
Table 13-5. SPIBR Register Field Descriptions
Field Description
6:4
SPPR[2:0]
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in Table 13-6 . The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
drives the input of the SPI baud rate divider (see Figure 13-15 ). See Section 13.4.6, “SPI Baud Rate Generation ,”
for details.
2:0
SPR[2:0]
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table 13-7 . The input to this divider comes from the SPI baud rate prescaler (see Figure 13-15 ). See
Section 13.4.6, “SPI Baud Rate Generation ,” for details.
Table 13-6. SPI Baud Rate Prescaler Divisor
SPPR2:SPPR1:SPPR0 Prescaler Divisor
0:0:0 1
0:0:1 2
0:1:0 3
0:1:1 4
1:0:0 5
1:0:1 6
1:1:0 7
1:1:1 8
Table 13-4. Bidirectional Pin Configurations
Pin Mode SPC0 BIDIROE MISO MOSI