Freescale Semiconductor HCS08 Series, Reference Manual

Page: 16 / 306

MC9S08JS16 MCU Series Reference Manual, Rev. 4
16 Freescale Semiconductor
15.3.13Endpoint Control Register (EPCTLn, n=0-6) .................................................................258
15.4 Functional Description ..................................................................................................................259
15.4.1 Block Descriptions ..........................................................................................................259
15.4.2 Buffer Descriptor Table (BDT) .......................................................................................264
15.4.3 USB Transactions ...........................................................................................................267
15.4.4 USB Packet Processing ...................................................................................................269
15.4.5 Start of Frame Processing ...............................................................................................270
15.4.6 Suspend/Resume .............................................................................................................271
15.4.7 Resets ..............................................................................................................................272
15.4.8 Interrupts .........................................................................................................................273
Chapter 16
Cyclic Redundancy Check Generator (S08CRCV2)
16.1 Introduction ...................................................................................................................................275
16.1.1 Features ...........................................................................................................................277
16.1.2 Modes of Operation ........................................................................................................277
16.1.3 Block Diagram ................................................................................................................278
16.2 External Signal Description ..........................................................................................................278
16.3 Register Definition .......................................................................................................................278
16.3.1 Memory Map ..................................................................................................................278
16.3.2 Register Descriptions ......................................................................................................279
16.4 Functional Description ..................................................................................................................280
16.4.1 ITU-T (CCITT) Recommendations & Expected CRC Results ......................................280
16.5 Initialization Information ..............................................................................................................281
Chapter 17
Development Support
17.1 Introduction ...................................................................................................................................283
17.1.1 Features ...........................................................................................................................284
17.2 Background Debug Controller (BDC) ..........................................................................................284
17.2.1 BKGD Pin Description ...................................................................................................285
17.2.2 Communication Details ..................................................................................................286
17.2.3 BDC Commands .............................................................................................................289
17.2.4 BDC Hardware Breakpoint .............................................................................................292
17.3 On-Chip Debug System (DBG) ....................................................................................................293
17.3.1 Comparators A and B .....................................................................................................293
17.3.2 Bus Capture Information and FIFO Operation ...............................................................293
17.3.3 Change-of-Flow Information ..........................................................................................294
17.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................294
17.3.5 Trigger Modes .................................................................................................................295
17.3.6 Hardware Breakpoints ....................................................................................................297
17.4 Register Definition ........................................................................................................................297
17.4.1 BDC Registers and Control Bits .....................................................................................297
17.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................299
17.4.3 DBG Registers and Control Bits .....................................................................................300