Chapter 5 Resets, Interrupts, and System Configuration
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor
75
5.7.6
Flash Protection Defeat Register (FPROTD)
5.7.7
SIGNATURE Register (SIGNATURE)
Table 5-7. SOPT2 Register Field Descriptions
Field
Description
7
COPCLKS
COP Watchdog Clock Select
— This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 kHz clock is source to COP.
1 Bus clock is source to COP.
6
COPW
COP Window
— This write-once bit selects the COP operation mode. When set, the 0x55–0xAA write sequence
to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the
first 75% of the selected period will reset the MCU.
0 Normal COP operation.
1 Window COP operation.
2
SPIFE
SPI1 Ports Input Filter Enable
0 Disable input filter on SPI port pins to allow for higher maximum SPI baud rate.
1 Enable input filter on SPI port pins to eliminate noise and restrict maximum SPI baud rate.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Bit0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-7. Flash Protection Defeat Register (FPROTD)
Table 5-8. FPROTD Register Field Descriptions
Field
Description
0
Protected flash section can be disabled by write 0x55 and 0xAA back to back to the address of FPROTD first,
then set bit FPDIS = 1 in FPROT register. This bit set to 1only after write 0x55 and 0xAA back to back successfully
that means FPDIS can be set to 1. Any write operation, will clear this bit except 0x55–AA write squence.
0 The bit FPDIS in FPROT can not be set to 1.
1 The bit FPDIS in FPROT can be set to 1.
7
6
5
4
3
2
1
0
R
SIGNATURE semaphore
W
POR
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-8. SIGNATURE Register (SIGNATURE)
Summary of Contents for HCS08 Series
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