16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor
199
Data may be read from SPIDH:SPIDL any time after SPRF is set and before another transfer is finished.
Failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun
condition and the data from the new transfer is lost.
In 8-bit mode, only SPIDL is available. Reads of SPIDH will return all 0s. Writes to SPIDH will be
ignored.
In 16-bit mode, reading either byte (SPIDH or SPIDL) latches the contents of both bytes into a buffer
where they remain latched until the other byte is read. Writing to either byte (SPIDH or SPIDL) latches
the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value
into the transmit data buffer.
13.3.6
SPI Match Registers (SPIMH:SPIML)
These read/write registers contain the hardware compare value, which sets the SPI match flag (SPMF)
when the value received in the SPI receive data buffer equals the value in the SPIMH:SPIML registers.
In 8-bit mode, only SPIML is available. Reads of SPIMH will return all 0s. Writes to SPIMH will be
ignored.
In 16-bit mode, reading either byte (SPIMH or SPIML) latches the contents of both bytes into a buffer
where they remain latched until the other byte is read. Writing to either byte (SPIMH or SPIML) latches
the value into a buffer. When both bytes have been written, they are transferred as a coherent value into
the SPI match registers.
13.4
Functional Description
13.4.1
General
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While the SPE
bit is set, the four associated SPI port pins are dedicated to the SPI function as:
•
Slave select (SS)
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Reset
0
0
0
0
0
0
0
0
Figure 13-11. SPI Match Register High (SPIMH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 13-12. SPI Match Register Low (SPIML)
Summary of Contents for HCS08 Series
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