Freescale Semiconductor HCS08 Series, Reference Manual

Page: 71 / 306

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 71
5.7.2 System Reset Status Register (SRS)
This register includes seven read-only status flags to indicate the source of the most recent reset. When a
debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will
be set. Writing any value to this register address causes a COP reset when the COP is enabled except for
the values 0x55 and 0xAA. Writing a 0x55
—
0xAA sequence to this address clears the COP watchdog timer
without affecting the contents of this register. The reset state of these bits depends on what caused the
MCU to reset.
3
IRQF
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
2
IRQACK
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
1
IRQIE
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
0
IRQMOD
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. See Section 5.5.2.2, “Edge and Level Sensitivity ,” for more details.
0 IRQ event on falling/rising edges only.
1 IRQ event on falling/rising edges and low/high levels.
7 6 5 4 3 2 1 0
R POR PIN COP ILOP ILAD LOC LVD —
W Writing any value to SRS address clears COP watchdog timer.
POR 1 0 0 0 0 0 1 0
LVR:
U 0 0 0 0 0 1 0
Any other
reset:
0
(1) (1) (1)
0
(1)
0 0
U = Unaffected by reset
1
Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset will be cleared.
Figure 5-3. System Reset Status (SRS)
Table 5-2. IRQSC Register Field Descriptions (continued)
Field Description