Freescale Semiconductor HCS08 Series Reference Manual Download Page 86

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Chapter 6 Parallel Input/Output

MC9S08JS16 MCU Series Reference Manual, Rev. 4

Freescale Semiconductor

Table 6-10. PTBDS Register Field Descriptions

Field

Description

5:0

PTBDS[5:1]

Output Drive Strength Selection for Port B Bits

— Each of these control bits selects between low and high

output drive for the associated PTB pin.
0 Low output drive enabled for port B bit n.
1 High output drive enabled for port B bit n.

Summary of Contents for HCS08 Series

Page 1: ...C9S08JS8L Reference Manual MC9S08JS16RM Rev 4 4 2009 Related Documentation MC9S08JS16 Data Sheet Contains pin assignments and diagrams all electrical specifications and mechanical drawing outlines Fin...

Page 2: ......

Page 3: ...nd up to 6 additional endpoints SPI One 8 or 16 bit selectable serial peripheral interface module with a receive data buffer hardware match function SCI One serial communication interface module with...

Page 4: ......

Page 5: ...MC9S08JS16 MCU Series Reference Manual Covers MC9S08JS16 MC9S08JS8 MC9S08JS16L MC9S08JS8L MC9S08JS16RM Rev 4 4 2009...

Page 6: ...n Date Description of Changes 1 8 27 2008 Initial public release 2 12 17 2008 Changed the content of register at address 0xFFAE and 0xFFAF in Table 4 4 and added the description of factory trim value...

Page 7: ...ntral Processor Unit S08CPUV2 87 Chapter 8 Keyboard Interrupt S08KBIV2 107 Chapter 9 Multi Purpose Clock Generator S08MCGV1 115 Chapter 10 Modulo Timer S08MTIMV1 147 Chapter 11 Real Time Counter S08RT...

Page 8: ......

Page 9: ...in 24 2 3 4 Background Mode Select BKGD MS 25 2 3 5 Bootloader Mode Select BLMS 26 2 3 6 USB Data Pins USBDP USBDN 26 2 3 7 General Purpose I O and Peripheral Ports 26 Chapter 3 Modes of Operation 3 1...

Page 10: ...mmand Register FCMD 61 Chapter 5 Resets Interrupts and System Configuration 5 1 Introduction 63 5 2 Features 63 5 3 MCU Reset 63 5 4 Computer Operating Properly COP Watchdog 64 5 5 Interrupts 65 5 5 1...

Page 11: ...6 5 3 Port B I O Registers PTBD and PTBDD 84 6 5 4 Port B Pin Control Registers PTBPE PTBSE PTBDS 84 Chapter 7 Central Processor Unit S08CPUV2 7 1 Introduction 87 7 1 1 Features 87 7 2 Programmer s Mo...

Page 12: ...9 1 Introduction 115 9 1 1 Features 117 9 1 2 Modes of Operation 119 9 2 External Signal Description 119 9 3 Register Definition 120 9 3 1 MCG Control Register 1 MCGC1 120 9 3 2 MCG Control Register...

Page 13: ...gnal Description 160 11 3 Register Definition 160 11 3 1 RTC Status and Control Register RTCSC 161 11 3 2 RTC Counter Register RTCCNT 162 11 3 3 RTC Modulo Register RTCMOD 162 11 4 Functional Descript...

Page 14: ...1 SPIC1 193 13 3 2 SPI Control Register 2 SPIC2 195 13 3 3 SPI Baud Rate Register SPIBR 196 13 3 4 SPI Status Register SPIS 197 13 3 5 SPI Data Registers SPIDH SPIDL 198 13 3 6 SPI Match Registers SPI...

Page 15: ...peration 239 Chapter 15 Universal Serial Bus Device Controller S08USBV1 15 1 Introduction 243 15 1 1 Clocking Requirements 243 15 1 2 Current Consumption in USB Suspend 243 15 1 3 3 3 V Regulator 243...

Page 16: ...2 Register Descriptions 279 16 4 Functional Description 280 16 4 1 ITU T CCITT Recommendations Expected CRC Results 280 16 5 Initialization Information 281 Chapter 17 Development Support 17 1 Introduc...

Page 17: ...ge above 3 9 V while MC9S08JS16L and MC9S08JS8L support USB bootloader function at 3 3 V Disable internal USB voltage regulator and apply 3 3 V to the VUSB33 pin when using MC9S08JS16L and MC9S08JS8L...

Page 18: ...KBIPEn 1 and associated pin is configured to enable the pullup device KBEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPT...

Page 19: ...terrupt KBI 2 Multi Purpose Clock Generator MCG 1 Real Time Counter RTC 1 Serial Communications Interface SCI 4 Serial Peripheral Interface SPI16 1 Modulo Timer MTIM 1 Timer Pulse Width Modulator TPM...

Page 20: ...for more information regarding the use of MCGIRCLK MCGERCLK This is the external reference clock and can be selected as the clock source of RTC module Section 9 4 6 External Reference Clock explains t...

Page 21: ...and detailed discussion of signals 2 2 Device Pin Assignment Figure 2 1 MC9S08JS16 Series in 24 pin QFN Package USBDN PTB3 BLMS 1 2 3 4 5 PTA0 KBIP0 TPMCH0 8 10 11 7 17 23 PTB2 BKGD MS 13 14 15 16 22...

Page 22: ...ns Figure 2 3 shows pin connections that are common to almost all MC9S08JS16 series application systems 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PTA3 KBIP3 SPSCK PTA4 KBIP4 SS USBDP USBDN VU...

Page 23: ...SBDP 5 VBUS is a 5 0 V supply from upstream port that can be used for USB operation 6 USBDP and USBDN are powered by the 3 3 V regulator 7 For USB operation an external crystal with a value of 2 MHz o...

Page 24: ...a crystal or ceramic resonator Rather than a crystal or ceramic resonator an external oscillator can be connected to the EXTAL input pin RS when used and RF must be low inductance resistors such as c...

Page 25: ...SBDFR for details the PTB2 BKGD MS pin functions as a mode select pin Immediately after reset rises the pin functions as the background pin and can be used for background debug communication When enab...

Page 26: ...s available 2 3 7 General Purpose I O and Peripheral Ports The MC9S08JS16 series of MCUs supports up to 14 general purpose I O pins including two output only pins which are shared with on chip periphe...

Page 27: ...ority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module All modules that share a pin must be disabled before another module is enabled 5...

Page 28: ...Chapter 2 Pins and Connections MC9S08JS16 MCU Series Reference Manual Rev 4 28 Freescale Semiconductor...

Page 29: ...he MC9S08JS16 series This mode is selected upon the MCU exiting reset if the BKGD MS pin is high In this mode the CPU executes code from internal memory with execution beginning at the address fetched...

Page 30: ...for the first time When the MC9S08JS16 series devices are shipped from the Freescale factory the flash program memory is erased by default unless specifically noted so there is no program that could...

Page 31: ...e real time clock RTC interrupt the USB resume interrupt LVD IRQ KBI or the SCI If stop3 is exited by the RESET pin then the MCU is reset and operation will resume after taking the reset vector Exit b...

Page 32: ...und commands are available 3 6 2 Stop2 Mode Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3 1 Most of the internal circuitry of the MCU is powered off in...

Page 33: ...background debug logic continue to operate clocks to the peripheral systems are halted to reduce power consumption Refer to Section 3 6 2 Stop2 Mode and Section 3 6 1 Stop3 Mode for specific informati...

Page 34: ...Chapter 3 Modes of Operation MC9S08JS16 MCU Series Reference Manual Rev 4 34 Freescale Semiconductor...

Page 35: ...for the MC9S08JS16 series On chip memory in the MC9S08JS16 series of MCUs consists of RAM flash program memory for nonvolatile data storage plus I O and control status registers The registers are div...

Page 36: ...m Configuration DIRECT PAGE REGISTERS RAM HIGH PAGE REGISTERS 512 BYTES 0x0000 0x007F 0x0080 0x027F 0x1800 0x17FF 0x185F 0xFFFF 0x0280 MC9S08JS16 MC9S08JS16L FLASH 16 384 BYTES 0x1860 UNIMPLEMENTED 0x...

Page 37: ...using these locations if the code will be ported to other MCUs 0xFFC4 FFC5 RTC Vrtc 0xFFC6 FFC7 Unused vector space 0xFFC8 FFC9 Unused vector space 0xFFCA FFCB MTIM Vmtim 0xFFCC FFCD KBI Vkeyboard 0x...

Page 38: ...ory they must be erased and programmed like other flash memory locations Direct page registers can be accessed with efficient direct addressing mode instructions Bit manipulation instructions can be u...

Page 39: ...2 1 Bit 0 0x0015 TPMC0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0 0x0016 TPMC0VH Bit 15 14 13 12 11 10 9 Bit 8 0x0017 TPMC0VL Bit 7 6 5 4 3 2 1 Bit 0 0x0018 TPMC1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0 0x...

Page 40: ...1 0x0057 Reserved 0x0058 PERID 0 0 ID5 ID4 ID3 ID2 ID1 ID0 0x0059 IDCOMP 1 1 NID5 NID4 NID3 NID2 NID1 NID0 0x005A REV REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 0x005B 0x005E Reserved 0x005F Reserved 0x0...

Page 41: ...SBDFR 0 0 0 0 0 0 0 BDFR 0x1802 SOPT1 COPT STOPE 1 0 BLMSS BKGDPE RSTPE 0x1803 SOPT2 COPCLKS COPW 0 0 0 SPIFE 0 0 0x1804 Reserved 0x1805 Reserved 0x1806 SDIDH ID11 ID10 ID9 ID8 0x1807 SDIDL ID7 ID6 ID...

Page 42: ...to 0x80 and the FTRIM bit in the MCGSC register will be reset to 0 0x1819 0x181F Reserved 0x1820 FCDIV DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 0x1821 FOPT KEYEN FNORED 0 0 0 0 SEC01 SEC00 0x1822 Re...

Page 43: ...m variables in this area of RAM is preferred The RAM retains data when the MCU is in low power wait stop2 or stop3 mode At power on the contents of RAM are uninitialized RAM data is unaffected by any...

Page 44: ...s a host USB device Working with the PC GUI the user can Mass erase entire flash array Partial erase flash array erase all flash blocks except for the first 1 KB of flash Program flash Reset MCU NOTE...

Page 45: ...ot equal to 0x00 or 0xFF then the bootloader mode is entered 3 When BLMS pin and BKGD MS are high during power on reset POR a CHECKSUM BYPASS flash location is examined If it is equal to 0xFF a flash...

Page 46: ...sh Memory Map The general flash memory map of bootloader is shown in Figure 4 2 Flash block checksum stores in 0xFFB8 checksum high byte and 0xFFB9 checksum low byte Checksum bypass information stores...

Page 47: ...CRC and re program the CRC checksum to ensure reliable entry after a POR 4 5 4 Bootloader Operation This section describes the bootloader mechanism and bootloader flow chart The bootloader software is...

Page 48: ...in their application code to set the SIGNATURE to 0xC3 and initiate a reset if they want to re enter bootloader mode after a successful user code has been programmed Alternatively BKGD mode can be en...

Page 49: ...User code executed YES Jump to bootloader entry CMD Mass erase NO NO Initial bus frequency to 24 MHz Initial USB Waiting for CMD CMD Program Flash CMD Reset Put Pass Fail on stack YES Put Pass Fail on...

Page 50: ...ature Flexible block protection Security feature for flash and RAM Auto power down for low frequency read accesses 4 6 2 Program and Erase Time Before any program or erase command can be accepted the...

Page 51: ...he flash 2 Write the command code for the desired command to FCMD The five valid commands are blank check 0x05 byte program 0x20 burst program 0x25 page erase 0x40 and mass erase 0x41 The command code...

Page 52: ...off When a burst program command is issued the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met The next burst program co...

Page 53: ...andard time instead of the burst time This is because the high voltage to the array must be disabled and then enabled again If a new burst command has not been queued before the current command comple...

Page 54: ...CU is secured The background debug controller can only do blank check and mass erase commands when the MCU is secure Writing 0 to FCBEF to cancel a partial command 4 6 6 Flash Block Protection The blo...

Page 55: ...ected by programming the NVPROT register located at address 0xFFBD All of the interrupt vectors memory locations 0xFFC0 0xFFFD are redirected though the reset vector 0xFFFE FFFF is not For example if...

Page 56: ...key values to the NVBACKKEY through NVBACKKEY 7 locations These writes must be done in order starting with the value for NVBACKKEY and ending with NVBACKKEY 7 STHX must not be used for these writes b...

Page 57: ...1 0 R DIVLD PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 7 Flash Clock Divider Register FCDIV Table 4 7 FCDIV Register Field Descriptions Field Descr...

Page 58: ...ash Options Register FOPT Table 4 9 FOPT Register Field Descriptions Field Description 7 KEYEN Backdoor Key Mechanism Enable When this bit is 0 the backdoor key mechanism cannot be used to disengage s...

Page 59: ...0 secure 0 1 secure 1 0 unsecured 1 1 secure 7 6 5 4 3 2 1 0 R 0 0 KEYACC 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 9 Flash Configuration Register FCNFG Table 4 11 FCNFG Reg...

Page 60: ...tions Field Description 7 FCBEF Flash Command Buffer Empty Flag The FCBEF bit is used to launch commands It also indicates that the command buffer is empty so that a new command sequence can be execut...

Page 61: ...y writing a 1 to FACCERR Writing a 0 to FACCERR has no meaning or effect 0 No access error 1 An access error has occurred 2 FBLANK Flash Verified as All Blank erased Flag FBLANK is set automatically a...

Page 62: ...Chapter 4 Memory MC9S08JS16 MCU Series Reference Manual Rev 4 62 Freescale Semiconductor...

Page 63: ...s register SRS to indicate source of most recent reset Separate interrupt vectors for each module reduces polling overhead see Table 5 1 5 3 MCU Reset Resetting the MCU provides a way to start process...

Page 64: ...internal 1 kHz clock source With each clock source there are three associated time outs controlled by the COPT bits in SOPT1 Table 5 6 summaries the control functions of the COPCLKS and COPT bits The...

Page 65: ...g the I bit in the CCR to mask further interrupts Fetching the interrupt vector for the highest priority interrupt that is currently pending Filling the instruction queue with the first three bytes of...

Page 66: ...red before returning from the ISR Typically the flag must be cleared at the beginning of the ISR so that if another interrupt is generated by this same source it will be registered so it can be servic...

Page 67: ...enabling the interrupt 5 5 2 2 Edge and Level Sensitivity The IRQMOD control bit re configure the detection logic so it detects edge events and pin levels In this edge detection mode the IRQF status...

Page 68: ...program 21 0xFFD4 FFD5 Vscitx SCI TDRE TC TIE TCIE SCI transmit 20 0xFFD6 FFD7 Vscirx SCI IDLE RDRF ILIE RIE SCI receive 19 0xFFD8 FFD9 Vscierr SCI OR NF FE PF ORIE NFIE FEIE PFIE SCI error 18 to 12 0...

Page 69: ...eset Operation The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDRE to 1 The low voltage detection threshold is determined by the LVDV bit After an...

Page 70: ...to configure the IRQ function report status and acknowledge IRQ events 7 6 5 4 3 2 1 0 R 0 IRQPDD IRQEDG IRQPE IRQF 0 IRQIE IRQMOD W IRQACK Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 5 2...

Page 71: ...meaning or effect Reads always return 0 If edge and level detection is selected IRQMOD 1 IRQF cannot be cleared while the IRQ pin remains at its asserted level 1 IRQIE IRQ Interrupt Enable This read...

Page 72: ...not caused by COP timeout 1 Reset caused by COP timeout 4 ILOP Illegal Opcode Reset was caused by an attempt to execute an unimplemented or illegal opcode The STOP instruction is considered illegal i...

Page 73: ...nal debug host to force a target system reset Writing logic 1 to this bit forces an MCU reset This bit cannot be written from a user program R COPT STOPE 1 0 BLMSS BKGDPE RSTPE W Reset 1 1 0 1 0 0 1 u...

Page 74: ...ESET 0 PTB1 RESET pin functions as PTB1 1 PTB1 RESET pin functions as RESET Table 5 6 COP Configuration Options Control Bits Clock Source COP Window1 Opens COPW 1 1 Windowed COP operation requires the...

Page 75: ...2 SPIFE SPI1 Ports Input Filter Enable 0 Disable input filter on SPI port pins to allow for higher maximum SPI baud rate 1 Enable input filter on SPI port pins to eliminate noise and restrict maximum...

Page 76: ...ID11 ID10 ID9 ID8 W Reset 0 0 0 0 Unimplemented or Reserved Figure 5 9 System Device Identification Register High SDIDH Table 5 10 SDIDH Register Field Descriptions Field Description 7 4 Reserved Bits...

Page 77: ...s 0 low voltage warning is not present 1 low voltage warning is present or was present 6 LVWACK Low Voltage Warning Acknowledge If LVWF 1 a low voltage condition has occurred To acknowledge this low v...

Page 78: ...Voltage Detect Voltage Select This bit selects the low voltage detect LVD trip point setting It also selects the warning voltage range See Table 5 14 4 LVWV Low Voltage Warning Voltage Select This bit...

Page 79: ...ontrolled by the parallel I O All of the parallel I O pins are configured as inputs PTxDDn 0 The pin control functions for each pin are configured as follows slew rate control enabled PTxSEn 1 low dri...

Page 80: ...enabled for a pin all digital pin functions are disabled A read of the port data register returns a value of 0 for any bit which has shared analog functions enabled In general whenever a pin is shared...

Page 81: ...to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load Because of this the EMC emissions may be affected by enabling pins as high drive 6 4 Pin Behavior i...

Page 82: ...ld Description 7 0 PTAD 7 0 Port A Data Register Bits For port A pins that are inputs reads return the logic level on the pin For port A pins that are configured as outputs reads return the last value...

Page 83: ...SE0 W Reset 0 0 0 0 0 0 0 0 Figure 6 5 Output Slew Rate Control Enable for Port A PTASE Table 6 4 PTASE Register Field Descriptions Field Description 7 0 PTASE 7 0 Output Slew Rate Control Enable for...

Page 84: ...configured as outputs reads return the last value written to this register Writes are latched into all bits of this register For port B pins that are configured as outputs the logic level is driven ou...

Page 85: ...p device disabled for port B bit n 1 Internal pullup device enabled for port B bit n 7 6 5 4 3 2 1 0 R 0 0 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure...

Page 86: ...le 6 10 PTBDS Register Field Descriptions Field Description 5 0 PTBDS 5 1 Output Drive Strength Selection for Port B Bits Each of these control bits selects between low and high output drive for the a...

Page 87: ...to a single 64 Kbyte address space 16 bit stack pointer any size stack anywhere in 64 Kbyte address space 16 bit index register H X with powerful indexed addressing modes 8 bit accumulator A Many ins...

Page 88: ...8 bit registers H and X which often work together as a 16 bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address All indexed addressing mode instructi...

Page 89: ...with the M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low order half of the stack pointer 7 2 4 Program Counter PC The program counter is a 16 bit register that...

Page 90: ...on of the interrupt service routine is executed Interrupts are not recognized at the instruction boundary after any instruction that clears I CLI or TAP This ensures that the next instruction after a...

Page 91: ...erands needed to complete the instruction if any are located within CPU registers so the CPU does not need to access memory to get any operands 7 3 2 Relative Addressing Mode REL Relative addressing m...

Page 92: ...de is only used for MOV and CBEQ instructions 7 3 6 3 Indexed 8 Bit Offset IX1 This variation of indexed addressing uses the 16 bit value in the H X index register pair plus an unsigned 8 bit offset i...

Page 93: ...he reset pin is no longer asserted At the conclusion of a reset event the CPU performs a 6 cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparat...

Page 94: ...to the MCU through the background debug interface while the CPU is in wait mode CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be proc...

Page 95: ...ssing user instructions and enter the active background mode The only way to resume execution of the user program is through reset or by a host debug system issuing a GO TRACE1 or TAGGO serial command...

Page 96: ...ADD oprx8 X ADD X ADD oprx16 SP ADD oprx8 SP Add without Carry A A M IMM DIR EXT IX2 IX1 IX SP2 SP1 AB BB CB DB EB FB 9E DB 9E EB ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rf...

Page 97: ...if C 0 Same as BCC REL 24 rr 3 ppp BIH rel Branch if IRQ Pin High if IRQ pin 1 REL 2F rr 3 ppp BIL rel Branch if IRQ Pin Low if IRQ pin 0 REL 2E rr 3 ppp BIT opr8i BIT opr8a BIT opr16a BIT oprx16 X B...

Page 98: ...b7 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp BSR rel Branch to Subroutine PC PC 0x0002 push PCL SP SP 0x0001 push PCH SP SP 0x000...

Page 99: ...CCR Updated But Operands Not Changed IMM DIR EXT IX2 IX1 IX SP2 SP1 A3 B3 C3 D3 E3 F3 9E D3 9E E3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp DAA Decimal Adjust...

Page 100: ...h ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 LDHX opr16i LDHX opr8a LDHX opr16a LDHX X LDHX oprx16 X LDHX oprx8 X LDHX oprx8 SP Load Index Register H X H X M M 0x0001 I...

Page 101: ...IX1 IX SP2 SP1 AA BA CA DA EA FA 9E DA 9E EA ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 PSHA Push Accumulator onto Stack Push A SP SP 0x0001 INH 87 2 sp PSHH P...

Page 102: ...EI Set Interrupt Mask Bit I 1 INH 9B 1 p 1 STA opr8a STA opr16a STA oprx16 X STA oprx8 X STA X STA oprx16 SP STA oprx8 SP Store Accumulator in Memory M A DIR EXT IX2 IX1 IX SP2 SP1 B7 C7 D7 E7 F7 9E D...

Page 103: ...Interrupt Vector High Byte PCL Interrupt Vector Low Byte INH 83 11 sssssvvfppp 1 TAP Transfer Accumulator to CCR CCR A INH 84 1 p TAX Transfer Accumulator to X Index Register Low X A INH 97 1 p TPA Tr...

Page 104: ...es PC Program counter PCH Program counter high byte PCL Program counter low byte rel Relative program counter offset byte SP Stack pointer SPL Stack pointer low byte X Index register low byte Logical...

Page 105: ...X 08 5 BRSET4 3 DIR 18 5 BSET4 2 DIR 28 3 BHCC 2 REL 38 5 LSL 2 DIR 48 1 LSLA 1 INH 58 1 LSLX 1 INH 68 5 LSL 2 IX1 78 4 LSL 1 IX 88 3 PULX 1 INH 98 1 CLC 1 INH A8 2 EOR 2 IMM B8 3 EOR 2 DIR C8 4 EOR 3...

Page 106: ...1 9E6A 6 DEC 3 SP1 9EDA 5 ORA 4 SP2 9EEA 4 ORA 3 SP1 9E6B 8 DBNZ 4 SP1 9EDB 5 ADD 4 SP2 9EEB 4 ADD 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 LDHX 2 IX 9EBE 6 LDHX 4 IX2 9ECE 5 LDHX 3 IX1 9EDE 5 L...

Page 107: ...16 series devices contain one KBI module with up to eight interrupt sources NOTE When enabling the KBI pin for use the KBF will be set and must be cleared prior to enabling the interrupt When configur...

Page 108: ...s configured to enable the pullup device KBEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MA...

Page 109: ...e an enabled KBI pin KBPEx 1 can be used to bring the MCU out of wait mode if the KBI interrupt is enabled KBIE 1 8 1 2 2 KBI in Stop Modes The KBI operates asynchronously in stop3 mode if enabled bef...

Page 110: ...bit pin enable register An 8 bit edge select register Refer to the direct page register summary in the Chapter 4 Memory for the absolute address assignments for all KBI registers This section refers t...

Page 111: ...etected 2 KBACK Keyboard Acknowledge Writing a 1 to KBACK is part of the flag clearing mechanism KBACK always reads as 0 1 KBIE Keyboard Interrupt Enable KBIE determines whether a keyboard interrupt i...

Page 112: ...upt KBIPEn 1 input signal is seen as a logic 1 the deasserted level during one bus cycle and then a logic 0 the asserted level during the next cycle A rising edge is detected when the input signal is...

Page 113: ...s used to select whether the resistor is a pullup KBEDGn 0 or a pulldown KBEDGn 1 8 4 4 KBI Initialization When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interru...

Page 114: ...Keyboard Interrupt S08KBIV2 MC9S08JS16 MCU Series Reference Manual Rev 4 114 Freescale Semiconductor...

Page 115: ...e clock The module can select either of the FLL or PLL clocks and either of the internal or external reference clocks as a source for the MCU system clock Whichever clock source is chosen it is passed...

Page 116: ...enable the pullup device KBEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VOLTAG...

Page 117: ...PLL Voltage controlled oscillator VCO Modulo VCO frequency divider Phase Frequency detector Integrated loop filter Lock detector with interrupt capability Internal reference clock Nine trim bits for...

Page 118: ...IM External Oscillator IREFS XOSC CLKS n 0 7 2n n 0 3 2n Internal Reference Clock BDIV 9 MCGLCLK MCGOUT MCGIRCLK EREFS RANGE EREFSTEN HGO IREFSTEN MCGERCLK LP MCGFFCLK DCOOUT FLL RDIV_CLK PLL VDIV 4 8...

Page 119: ...ion for the MCG FLL Engaged Internal FEI FLL Engaged External FEE FLL Bypassed Internal FBI FLL Bypassed External FBE PLL Engaged External PEE PLL Bypassed External PBE Bypassed Low Power Internal BLP...

Page 120: ...ed the resulting frequency must be in the range 1 MHz to 2 MHz 000 Encoding 0 Divides reference clock by 1 reset default 001 Encoding 1 Divides reference clock by 2 010 Encoding 2 Divides reference cl...

Page 121: ...ock source 0 Low frequency range selected for the external oscillator of 32 kHz to 100 kHz 32 kHz to 1 MHz for external clock source 4 HGO High Gain Oscillator Select Controls the external oscillator...

Page 122: ...etting Controls the internal reference clock frequency by controlling the internal reference clock period The TRIM bits are binary weighted i e bit 1 will adjust twice as much as bit 0 Increasing the...

Page 123: ...ntil the FLL or PLL has reacquired lock Stop mode entry will also cause the lock status bit to clear and stay cleared until the FLL or PLL has reacquired lock Entry into BLPI or BLPE mode will also ca...

Page 124: ...y the smallest amount possible If an FTRIM value stored in nonvolatile memory is to be used it s the user s responsibility to copy that value from the nonvolatile memory location to this register s FT...

Page 125: ...0 Clock monitor is disabled 1 Generate a reset request on loss of external clock 3 0 VDIV VCO Divider Selects the amount to divide down the VCO output of PLL The VDIV bits establish the multiplicatio...

Page 126: ...hile in stop Stop PLL Bypassed External PBE PLL Engaged External PEE FLL Engaged External FEE FLL Engaged Internal FEI FLL Bypassed External FBE FLL Bypassed Internal FBI IREFS 1 CLKS 00 PLLS 0 IREFS...

Page 127: ...ur CLKS bits are written to 00 IREFS bit is written to 0 PLLS bit is written to 0 RDIV bits are written to divide reference clock to be within the range of 31 25 kHz to 39 0625 kHz In FLL engaged exte...

Page 128: ...ernal reference clock The external reference clock which is enabled can be an external crystal resonator or it can be another external clock source The FLL clock is controlled by the external referenc...

Page 129: ...rom the external reference clock The external reference clock which is enabled can be an external crystal resonator or it can be another external clock source The PLL clock frequency locks to a multip...

Page 130: ...EFS bit can be changed at anytime but the RDIV bits must be changed simultaneously so that the reference frequency stays in the range required by the state of the PLLS bit 31 25 kHz to 39 0625 kHz if...

Page 131: ...other resets Until MCGIRCLK is trimmed programming low reference divider RDIV factors may result in MCGOUT frequencies that exceed the maximum chip level frequency and violate the chip level clock tim...

Page 132: ...POR the internal reference will require trimming to guarantee an accurate clock Freescale recommends using FLASH location 0xFFAE for storing the fine trim bit FTRIM in the MCGSC register and 0xFFAF f...

Page 133: ...red and the LOCK bit is set before moving on If in FBE mode check to make sure the IREFST bit is cleared the LOCK bit is set and the CLKST bits have changed to 10 indicating the external reference clo...

Page 134: ...will be described Then a flowchart will be included which illustrates the sequence 1 First FEI must transition to FBE mode a MCGC2 0x36 00110110 BDIV bits 7 and 6 set to 00 or divide by 1 RANGE bit 5...

Page 135: ...matter because both the FLL and PLL are disabled Changing them only sets up the the dividers for PLL usage in PBE mode c BLPE PBE MCGC3 0x44 01000100 PLLS bit 6 set to 1 selects the PLL In BLPE mode c...

Page 136: ...EE Mode Transition using a 4 MHz crystal MCGC2 0x36 CHECK OSCINIT 1 MCGC1 0xB8 CHECK IREFST 0 CHECK CLKST 10 ENTER BLPE MODE MCGC2 0x3E LP 1 MCGC1 0x90 MCGC3 0x44 IN BLPE MODE LP 1 MCGC2 0x36 LP 0 CHE...

Page 137: ...guration of the RDIV does not matter because both the FLL and PLL are disabled Changing them only sets up the dividers for FLL usage in FBE mode c BLPE FBE MCGC3 0x04 00000100 PLLS bit 6 clear to 0 to...

Page 138: ...t 3 in MCGSC is 1 Figure 9 10 Flowchart of PEE to BLPI Mode Transition using a 4 MHz crystal MCGC1 0x90 CHECK CLKST 10 MCGC2 0x3E MCGC1 0x44 CHECK IREFST 0 CHECK CLKST 01 CONTINUE IN BLPI MODE START I...

Page 139: ...36 00110110 RANGE bit 5 set to 1 because the frequency of 4 MHz is within the high frequency range HGO bit 4 set to 1 to configure external oscillator for high gain operation EREFS bit 2 set to 1 beca...

Page 140: ...bus frequency of 8 MHz This example is similar to example number one except that in this case the frequency of the external crystal is 8 MHz instead of 4 MHz Special consideration must be taken with t...

Page 141: ...tion EREFS bit 2 set to 1 because a crystal is being used ERCLKEN bit 1 set to 1 to ensure the external reference clock is active b Loop until OSCINIT bit 1 in MCGSC is 1 indicating the crystal select...

Page 142: ...e VDIV bits does not matter because the PLL is disabled Changing them only sets up the multiply value for PLL usage in PBE mode e Loop until PLLST bit 5 in MCGSC is set indicating that the current sou...

Page 143: ...12 Flowchart of FEI to PEE Mode Transition using a 8 MHz crystal MCGC2 0x36 CHECK OSCINIT 1 MCGC1 0xB8 CHECK IREFST 0 CHECK CLKST 10 MCGC2 0x3E LP 1 MCGC1 0x98 MCGC3 0x44 MCGC2 0x36 LP 0 CHECK PLLST 1...

Page 144: ...In Example 5 Internal Reference Clock Trim this approach will be demonstrated After a trim value has been found for a device this value can be stored in FLASH memory to save the value If power is remo...

Page 145: ...it is recommended to trim using a reference divider value RDIV setting of twice the final value After the trim procedure is complete the reference divider can be restored This will prevent accidental...

Page 146: ...Multi Purpose Clock Generator S08MCGV1 MC9S08JS16 MCU Series Reference Manual Rev 4 146 Freescale Semiconductor...

Page 147: ...te as a free running counter or a modulo counter A timer overflow interrupt can be enabled to generate periodic interrupts for time based software loops Figure 10 1 shows the MC9S08JS16 series block d...

Page 148: ...KBEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VOLTAGE REGULATOR COP IRQ LVD L...

Page 149: ...e the MTIM can be used to bring the MCU out of wait mode if the timer overflow interrupt is enabled For lowest possible current consumption the MTIM should be stopped by software if not needed as an i...

Page 150: ...d by the bus clock Also variations in duty cycle and clock jitter must be accommodated Therefore the TCLK signal must be limited to one fourth of the bus frequency The TCLK pin can be muxed with a gen...

Page 151: ...summary in the Memory chapter of this data sheet for the absolute address assignments for all MTIM registers This section refers to registers and control bits only by their names and relative address...

Page 152: ...MOD register 0 MTIM counter has not reached the overflow value in the MTIM modulo register 1 MTIM counter has reached the overflow value in the MTIM modulo register 6 TOIE MTIM Overflow Interrupt Enab...

Page 153: ...Reset clears CLKS to 000 00 Encoding 0 Bus clock BUSCLK 01 Encoding 1 Fixed frequency clock XCLK 10 Encoding 3 External source TCLK pin falling edge 11 Encoding 4 External source TCLK pin rising edge...

Page 154: ...Field Description 7 0 COUNT MTIM Count These eight read only bits contain the current value of the 8 bit counter Writes have no effect to this register Reset clears the count to 0x00 7 6 5 4 3 2 1 0 R...

Page 155: ...rescale values are software selectable clock source divided by 1 2 4 8 16 32 64 128 or 256 The prescaler select bits PS 3 0 in MTIMSC select the desired prescale value If the counter is active TSTP 0...

Page 156: ...elected clock source could be any of the five possible choices The prescaler is set to PS 0010 or divide by 4 The modulo value in the MTIMMOD register is set to 0xAA When the counter MTIMCNT reaches t...

Page 157: ...RTC consists of one 8 bit counter one 8 bit comparator several binary based and decimal based prescaler dividers two clock sources and one programmable periodic interrupt This module can be used for t...

Page 158: ...BEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VOLTAGE REGULATOR COP IRQ LVD LOW...

Page 159: ...e interrupt is enabled For lowest possible current consumption the RTC should be stopped by software if not needed as an interrupt source during wait mode 11 1 2 2 Stop Modes The RTC continues to run...

Page 160: ...ister Refer to the direct page register summary in the memory section of this document for the absolute address assignments for all RTC registers This section refers to registers and control bits only...

Page 161: ...e RTC prescaler Changing the clock source clears the prescaler and RTCCNT counters When selecting a clock source ensure that the clock source is properly enabled if applicable to ensure correct operat...

Page 162: ...ck LPO the external clock ERCLK and the internal clock IRCLK The RTC clock select bits RTCLKS select the desired clock source If a different value is written to RTCLKS the prescaler and RTCCNT counter...

Page 163: ...ows for an interrupt to be generated when RTIF is set To enable the real time interrupt set the real time interrupt enable bit RTIE in RTCSC RTIF is cleared by writing a 1 to RTIF 11 4 1 RTC Operation...

Page 164: ...to initialize and configure the RTC module The example software is implemented in C language The example below shows how to implement time of day with the RTC using the 1 kHz clock source to achieve t...

Page 165: ...e Manual Rev 4 Freescale Semiconductor 165 RTCSC byte RTCSC byte 0x80 RTC interrupts every 1 Second Seconds 60 seconds in a minute if Seconds 59 Minutes Seconds 0 60 minutes in an hour if Minutes 59 H...

Page 166: ...Real Time Counter S08RTCV1 MC9S08JS16 MCU Series Reference Manual Rev 4 166 Freescale Semiconductor...

Page 167: ...t modulo based baud rate generator supports a broad range of standard baud rates beyond 115 2 kbaud Transmit and receive within the same SCI use a common baud rate and each SCI module has a separate b...

Page 168: ...ullup device KBEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VOLTAGE REGULATOR C...

Page 169: ...eceive overrun parity error framing error and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and checking Programmable 8 bit or 9 bi...

Page 170: ...8 7 6 5 4 3 2 1 0 L SCID Tx BUFFER WRITE ONLY INTERNAL BUS STOP 11 BIT TRANSMIT SHIFT REGISTER START SHIFT DIRECTION LSB 1 BAUD RATE CLOCK PARITY GENERATION TRANSMIT CONTROL SHIFT ENABLE PREAMBLE ALL...

Page 171: ...NAL BUS STOP 11 BIT RECEIVE SHIFT REGISTER START SHIFT DIRECTION LSB FROM RxD PIN RATE CLOCK Rx INTERRUPT REQUEST DATA RECOVERY DIVIDE 16 BAUD SINGLE WIRE LOOP CONTROL WAKEUP LOGIC ALL 1s MSB FROM TRA...

Page 172: ...o value so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled RE or TE bits in SCIC2 are written to 1 7 6 5 4 3 2 1 0 R LBKDIE RXEDGIE 0 S...

Page 173: ...6 SCISWAI SCI Stops in Wait Mode 0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU 1 SCI clocks freeze while CPU is in wait mode 5 RSRC Rece...

Page 174: ...en TDRE flag is 1 6 TCIE Transmission Complete Interrupt Enable for TC 0 Hardware interrupts from TC disabled use polling 1 Hardware interrupt requested when TC flag is 1 5 RIE Receiver Interrupt Enab...

Page 175: ...ignificant data bit in a character WAKE 1 address mark wakeup Application software sets RWU and normally a selected hardware condition automatically clears RWU Refer to Section 12 3 3 2 Receiver Wakeu...

Page 176: ...cter is all 1s these bit times and the stop bit time count toward the full character time of logic high 10 or 11 bit times depending on the M control bit needed for the receiver to detect an idle line...

Page 177: ...ct circuitry is enabled and a LIN break character is detected LBKDIF is cleared by writing a 1 to it 0 No LIN break character has been detected 1 LIN break character has been detected 6 RXEDGIF RxD Pi...

Page 178: ...le waiting for a start bit 1 SCI receiver active RxD input not idle 1 Setting RXINV inverts the RxD input for all cases data bits start and stop bits break and idle 7 6 5 4 3 2 1 0 R R8 T8 TXDIR TXINV...

Page 179: ...bus rate clock 4 TXINV1 Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Ena...

Page 180: ...in Figure 12 2 The transmitter output TxD idle state defaults to logic high TXINV 0 following reset The transmitter output is inverted by setting TXINV 1 The transmitter is enabled by setting the TE b...

Page 181: ...te 0 and then write 1 to the TE bit This action queues an idle character to be sent as soon as the shifter is available As long as the character in the shifter does not finish while TE 0 the SCI trans...

Page 182: ...the case of the start bit the bit is assumed to be 0 if at least two of the samples at RT3 RT5 and RT7 are 0 even if one or all of the samples taken at RT8 RT9 and RT10 are 1s If any sample in any bit...

Page 183: ...matically when the receiver detects a logic 1 in the most significant bit of a received character eighth bit in M 0 mode and ninth bit in M 1 mode Address mark wakeup allows messages to contain idle c...

Page 184: ...s already set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun OR flag gets set instead the data along with any associated NF FE or PF co...

Page 185: ...s sometimes used to check software independent of connections in the external system to help isolate system problems In this mode the transmitter output is internally connected to the receiver input a...

Page 186: ...Serial Communications Interface S08SCIV4 MC9S08JS16 MCU Series Reference Manual Rev 4 186 Freescale Semiconductor...

Page 187: ...or the receive data buffer The MC9S08JS16 series have one serial peripheral interface module SPI The four pins associated with SPI functionality are shared with PTA 4 1 See MC9S08JS16 Series Data Shee...

Page 188: ...pullup device KBEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VOLTAGE REGULATOR...

Page 189: ...ta transmission length Write SPIBR to set baud rate Write SPIMH SPIML to set hardware compare value that triggers SPMF optional when value in receive data buffer equals this value Module Use After SPI...

Page 190: ...the SPISWAI bit is set the SPI goes into a power conservative state with the SPI clock generation turned off If the SPI is configured as a master any transmission in progress stops but is resumed afte...

Page 191: ...central element of the SPI is the SPI shift register Data is written to the double buffered transmitter write to SPIDH SPIDL and gets transferred to the SPI shift register at the start of a data tran...

Page 192: ...ose port I O pins that are not controlled by the SPI SPI SHIFT REGISTER SHIFT CLOCK SHIFT DIRECTION Rx BUFFER FULL Tx BUFFER EMPTY SHIFT OUT SHIFT IN ENABLE SPI SYSTEM CLOCK LOGIC CLOCK GENERATOR BUS...

Page 193: ...de and slave mode is selected this pin becomes the bidirectional data I O pin SISO and the bidirectional mode output enable bit determines whether the pin acts as an input BIDIROE 0 or an output BIDIR...

Page 194: ...transmit data between SPI modules the SPI modules must have identical CPOL values This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device Ref...

Page 195: ...Enable When the SPI is configured for slave mode this bit has no meaning or effect The SS pin is the slave select input In master mode this bit determines how the SS pin is used refer to Table 13 2 f...

Page 196: ...escriptions Field Description 6 4 SPPR 2 0 SPI Baud Rate Prescale Divisor This 3 bit field selects one of eight divisors for the SPI baud rate prescaler as shown in Table 13 6 The input to this presca...

Page 197: ...Table 13 8 SPIS Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI...

Page 198: ...nsmit shift register For an idle SPI data written to SPIDH SPIDL is transferred to the shifter almost immediately so SPTEF is set within two bus cycles allowing a second data to be queued into the tra...

Page 199: ...registers contain the hardware compare value which sets the SPI match flag SPMF when the value received in the SPI receive data buffer equals the value in the SPIMH SPIML registers In 8 bit mode only...

Page 200: ...fers to the shift register The data begins shifting out on the MOSI pin under the control of the serial clock SPSCK The SPR2 SPR1 and SPR0 baud rate selection bits in conjunction with the SPPR2 SPPR1...

Page 201: ...must be low SS must remain low until the transmission is complete If SS goes high the SPI is forced into idle state The SS input also controls the serial data output pin if SS is high not selected the...

Page 202: ...ne byte SPIML Reads of SPIDH and SPIMH will return zero Writes to SPIDH and SPIMH will be ignored In 16 bit mode SPIMODE 1 the SPI Data Register is comprised of two bytes SPIDH and SPIDL Reading eithe...

Page 203: ...t lines show the order of SPI data bits depending on the setting in LSBFE Both variations of SPSCK polarity are shown but only one of these waveforms applies for a specific transfer depending on the v...

Page 204: ...mes are shown for reference with bit 1 starting as the slave is selected SS IN goes low and bit 8 ends at the last SPSCK edge The MSB first and LSB first lines show the order of SPI data bits dependin...

Page 205: ...SPR0 divide the output of the prescaler stage by 2 4 8 16 32 64 128 or 256 to get the internal SPI master mode bit rate clock The baud rate generator is activated only when the SPI is in the master mo...

Page 206: ...the MISO pin becomes serial data I O SISO pin for the slave mode The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI The direction of each serial I O pin depends on the BID...

Page 207: ...case the mode fault error function is inhibited and MODF remains cleared In case the SPI system is configured as a slave the SS pin is a dedicated input pin Mode fault error doesn t occur in slave mo...

Page 208: ...sly receive data from the master byte NOTE Care must be taken when expecting data from a master while the slave is in wait or stop3 mode Even though the shift register will continue to operate the res...

Page 209: ...its instead of using interrupts The SPI interrupt service routine ISR must check the flag bits to determine what event caused the interrupt The service routine must also clear the flag bit s before re...

Page 210: ...mmunication an initialization procedure must be carried out as follows 1 Update control register 1 SPIC1 to enable the SPI and to control interrupt enables This register also sets the SPI as master or...

Page 211: ...s start with most significant bit Table 13 11 SPIC2 0xC0 11000000 Bit 7 SPMIE 1 SPI hardware match interrupt enabled Bit 6 SPIMODE 1 Configures SPI for 16 bit mode Bit 5 0 Unimplemented Bit 4 MODFEN 0...

Page 212: ...the hardware match buffer In 8 bit mode writes to this register will be ignored Table 13 15 SPIML 0xXX Holds bits 0 7 of the hardware match buffer Table 13 16 SPIDH 0xxx In 16 bit mode this register h...

Page 213: ...ductor 213 Figure 13 16 Initialization Flowchart Example for SPI Master Device in 16 bit Mode INITIALIZE SPI SPIC1 0x54 SPIC2 0xC0 SPIBR 0x00 SPIMH 0xXX RESET YES READ SPMF WHILE SET TO CLEAR FLAG THE...

Page 214: ...16 Bit Serial Peripheral Interface S08SPI16V1 MC9S08JS16 MCU Series Reference Manual Rev 4 214 Freescale Semiconductor...

Page 215: ...e Section 9 4 7 Fixed Frequency Clock NOTE TCLK external input clock source for TPM and MTIM is referenced as TPMCLK in TPM chapter 14 2 Features The timer system in the MC9S08JS16 series include one...

Page 216: ...n can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VOLTAGE REGULATOR COP IRQ LVD LOW POW...

Page 217: ...turns the latched value of TPMCNTH L from the read buffer instead of the frozen TPM counter value In BDM mode a write to TPMSC TPMCNTH or TPMCNTL Clears this read coherency mechanism Does not clear th...

Page 218: ...MMODH L 1 6 Produces a near 100 duty cycle Produces 0 duty cycle TPMCnVH L is changed from 0x0000 to a non zero value7 Waits for the start of a new PWM period to begin using the new duty cycle setting...

Page 219: ...E to 0xFFFF Also when configuring the TPM modules it is best to write to TPMSC before TPMCnV as a write to TPMxSC resets the coherency mechanism on the TPMCnV registers 8 For more information refer to...

Page 220: ...ed PWM mode is selected input capture output compare and edge aligned PWM functions are not available on any channels of this TPM module When the microcontroller is in active BDM background or BDM for...

Page 221: ...tive This type of PWM signal is called center aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero This type of PWM is required for type...

Page 222: ...C INTER RUPT LOGIC CPWMS MS0B MS0A COUNTER RESET CLKSB CLKSA 1 2 4 8 16 32 64 BUS CLOCK FIXED SYSTEM CLOCK EXTERNAL CLOCK SYNC 16 BIT COMPARATOR 16 BIT LATCH CHANNEL 1 ELS1B ELS1A CH1IE CH1F INTERNAL...

Page 223: ...e specific chip implementation Refer to documentation for the full chip for details about reset states port connections and whether there is any pullup device on these pins TPM channel pins can be ass...

Page 224: ...the I O pin when ELSnB ELSnA 0 0 or when CLKSB CLKSA 0 0 so it normally reverts to general purpose I O control When CPWMS 1 and ELSnB ELSnA not 0 0 all channels within the TPM are configured for cent...

Page 225: ...e start of each new period TPMCNT 0x0000 and the pin is forced low when the channel value register matches the timer counter When ELSnA 1 the TPMCHn pin is forced low at the start of each new period T...

Page 226: ...Hn pin is set when the timer counter is counting down and the channel value register matches the timer counter If ELSnA 1 the corresponding TPMCHn pin is set when the timer counter is counting up and...

Page 227: ...F interrupts inhibited use for software polling 1 TOF interrupts enabled 5 CPWMS Center aligned PWM select When present this read write bit selects CPWM operating mode By default the TPM operates in u...

Page 228: ...omatically restarted by an MCU reset or any write to the timer status control register TPMSC Reset clears the TPM counter registers Writing any value to TPMCNTH or TPMCNTL also clears the TPM counter...

Page 229: ...gisters to 0x0000 which results in a free running timer counter modulo disabled Writing to either byte TPMMODH or TPMMODL latches the value into a buffer and the registers are updated with the value o...

Page 230: ...alue in the TPM channel n value registers When channel n is an edge aligned center aligned PWM channel and the duty cycle is set to 0 or 100 CHnF will not be set even when the value in the TPM counter...

Page 231: ...apture event select the level that will be driven in response to an output compare match or select the polarity of the PWM output Setting ELSnB ELSnA to 0 0 configures the related timer pin as a gener...

Page 232: ...KSB CLKSA 0 0 then the registers are updated when the second byte is written If CLKSB CLKSA not 0 0 and in output compare mode then the registers are updated after the second byte is written and on th...

Page 233: ...uences the way the main counter operates In CPWM mode the counter changes to an up down mode rather than the up counting mode used for general purpose timer functions The following sections describe t...

Page 234: ...pin was also being used as the timer external clock source It is the user s responsibility to avoid such settings The TPM channel could still be used in output compare mode for software timing functi...

Page 235: ...gisters determine the basic mode of operation for the corresponding channel Choices include input capture output compare and edge aligned PWM 14 6 2 1 Input Capture Mode With the input capture functio...

Page 236: ...e The output compare value in the TPM channel registers determines the pulse width duty cycle of the PWM signal Figure 14 15 The time between the modulus overflow and the output compare is the pulse w...

Page 237: ...rate 100 duty cycle This is not a significant limitation The resulting period would be much longer than required for normal applications TPMMODH TPMMODL 0x0000 is a special case that should not be use...

Page 238: ...PMMODL the TPM can optionally generate a TOF interrupt at the end of this count Writing to TPMSC cancels any values written to TPMMODH and or TPMMODL and resets the coherency mechanism for the modulo...

Page 239: ...to clear the interrupt flag before returning from the interrupt service routine TPM interrupt flags are cleared by a two step process including a read of the flag bit while it is set 1 followed by a w...

Page 240: ...eration 14 8 2 2 3 PWM End of Duty Cycle Events For channels configured for PWM operation there are two possibilities When the channel is configured for edge aligned PWM the channel flag gets set when...

Page 241: ...ite buffer at the next change of the TPM counter end of the prescaler counting after the second byte is written Instead the TPM v2 always updates these registers when their second byte is written Edge...

Page 242: ...at the middle of the current PWM period when the count reaches 0x0000 TPMxCnVH L is changed from a non zero value to 0x0000 SE110 TPM case 4 In this case the TPM v3 finishes the current PWM period usi...

Page 243: ...To achieve the 48 MHz clock rate the MCG must be configured properly for PLL engaged external PEE mode with an external crystal For USB operation examples of MCG configuration using PEE mode include...

Page 244: ...al Rev 4 244 Freescale Semiconductor Table 15 1 USBVREN Configuration USBVREN 3 3 V Regulator VDD Supply Voltage Range 0 External 3 3 V Regulator as input to VUSB33 pin VUSB33 VDD Supply Voltage 1 Int...

Page 245: ...up device KBEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VOLTAGE REGULATOR COP...

Page 246: ...ed as buffers for USB controller or extra system RAM resource USB reset options USB module reset generated by MCU Bus reset generated by the host which triggers a CPU interrupt Suspend and resume oper...

Page 247: ...bus is idle for 3 ms The device USB suspend mode current consumption level requirements are defined by the USB Specification Rev 2 0 500 A for low power and 2 5 mA for high power with remote wakeup e...

Page 248: ...o meet the USB Specification Rev 2 0 impedance requirement 15 2 3 VUSB33 VUSB33 is connected to the on chip 3 3 V voltage regulator VREG VUSB33 maintains an output voltage of 3 3 V and can only source...

Page 249: ...it has been set indicating a K state on the USB bus This bit must be set before entering low power stop3 mode only after SLEEPF 1 USB is entering suspend mode It must be cleared immediately after stop...

Page 250: ...r Reserved Figure 15 4 Peripheral ID Register PERID Table 15 4 PERID Field Descriptions Field Description 5 0 ID 5 0 Peripheral Configuration Number This number is set to 0x04 and indicates that the p...

Page 251: ...handshake has been sent 5 RESUMEF Resume Flag This bit is set 2 5 s after clocks to the USB module have restarted following resume signaling It can be used to indicate remote wakeup signaling on the...

Page 252: ...rite 0x00 to the address register and to enable endpoint 0 USBRSTF is set once a USB reset has been detected for 2 5 s It will not be asserted again until the USB reset condition has been removed and...

Page 253: ...Bit Stuff Error Flag A bit stuff error has been detected If set the corresponding packet will be rejected due to a bit stuff error 0 No bit stuff error detected 1 Bit stuff error flag set 5 BUFERRF B...

Page 254: ...ror detected 1 CRC5 error detected and the token packet was rejected 0 PIDERRF PID Error Flag The PID check failed 0 No PID check error detected 1 PID check error detected 7 6 5 4 3 2 1 0 R BTSERR 0 B...

Page 255: ...is processing the next Clearing the TOKDNEF bit in the INTSTAT register causes the SIE to update the STAT register with the contents of the next STAT value If the next data in the STAT FIFO holding re...

Page 256: ...informs the processor that the SIE has disabled packet transmission and reception Clearing this bit allows the SIE to continue token processing 0 Allows the SIE to continue token processing 1 Set by...

Page 257: ...e number The frame number registers require two 8 bit registers to implement The low order byte is contained in FRMNUML and the high order byte is contained in FRMNUMH These registers are updated with...

Page 258: ...0 0 0 0 0 0 0 Unimplemented or Reserved Figure 15 16 Frame Number Register High FRMNUMH Table 15 16 FRMNUMH Field Descriptions Field Description 2 0 FRM 10 8 Frame Number These bits represent the high...

Page 259: ...E is connected to the rest of the system via 1 EPSTALL Endpoint Stall When set this bit indicates that the endpoint is stalled This bit has priority over all other control bits in the endpoint control...

Page 260: ...tion When the buffer is configured as an IN buffer and the USB host requests a packet the SIE responds with a properly formatted data packet The transmitter logic is also used to generate responses to...

Page 261: ...mits data to and from buffers stored in the shared buffer memory The serial interface engine SIE uses a table of descriptors the Buffer Descriptor Table BDT which is also stored in the USB RAM to desc...

Page 262: ...B bus the firmware must configure the MCU for stop3 mode In standby mode the requirement is to maintain the USBDP pin voltage at 3 0 V to 3 6 V with a 900 worst case pullup Power off This mode is ente...

Page 263: ...can be enabled accordingly With self powered applications determining when a valid USB connection is made is different from that of bus powered applications In self powered applications VBUS sensing m...

Page 264: ...e BD entry and the data buffer are owned by the USB module The USB module now has full read and write access and the microcontroller must not modify the BD or its corresponding data buffer 15 4 2 1 Mu...

Page 265: ...USB module and the MCU The BDs have different meanings based on who is reading the BD in memory The USB module uses the data stored in the BDs to determine Who owns the buffer in system memory Data0...

Page 266: ...rally writes a 0 to this bit when it has completed a token The USB module ignores all other fields in the BD when OWN 0 Once the BD has been assigned to the USB module OWN 1 the MCU must not change it...

Page 267: ...oken would be processed BDTSTALL BDT Stall Setting this bit will cause the USB module to issue a STALL handshake if a token is received by the SIE that would use the BDT in this location The BDT is no...

Page 268: ...and will succeed In the second case of oversized data packets the USB specification assumes correct software drivers on both sides The overrun is not due to memory latency but to a lack of space to p...

Page 269: ...are supported on all endpoints Isochronous endpoints also can only specify packet sizes up to 64 bytes Firmware is also responsible for setting the appropriate bits in the BDT For most applications u...

Page 270: ...WN 1 For an IN data phase OUT status phase the host will send a zero byte packet to the device Firmware can verify completion of the data phase by verifying the received token in the BD on receipt of...

Page 271: ...y after the SLEEPF bit is set enables this asynchronous notification feature The USB resume signaling will then cause the LPRESF bit to be set indicating a low power SUSPEND resume which will wake the...

Page 272: ...period required by the USB Specification Rev 2 0 Section 7 1 7 7 and then clear it to 0 15 4 7 Resets The module supports multiple types of resets The first is a bus reset generated by the USB Host t...

Page 273: ...STALL The ERRSTAT interrupts carry information about specific types of errors which is needed on an application specific basis Using ERRSTAT an application can determine exactly why a packet transfer...

Page 274: ...Universal Serial Bus Device Controller S08USBV1 MC9S08JS16 MCU Series Reference Manual Rev 4 274 Freescale Semiconductor...

Page 275: ...chapter describes the cyclic redundancy check CRC generator module which uses the 16 bit CRC CCITT polynomial x16 x12 x5 1 to generate a CRC code for error detection The 16 bit code is calculated by 8...

Page 276: ...p device KBEDGn can be used to reconfigure the pullup as a pulldown device PTA2 KBIP2 MOSI PORT A HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT VOLTAGE REGULATOR COP I...

Page 277: ...errors Programmable initial seed value High speed CRC calculation 16 1 2 Modes of Operation This section defines the CRC operation in run wait and stop modes Run Mode This is the basic mode of operat...

Page 278: ...Block Diagram 16 2 External Signal Description There are no CRC signals that connect off chip 16 3 Register Definition 16 3 1 Memory Map Table 16 1 CRC Register Summary Name 7 6 5 4 3 2 1 0 CRCH offse...

Page 279: ...2 CRC Low Register CRCL 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure 16 3 CRC High Register CRCH Table 16 2 Register Field Descriptions Field...

Page 280: ...cond calculation can be read directly from CRCH CRCL After each byte has finished shifting a new CRC result will appear in CRCH CRCL and an additional byte may be written to the CRCL register to be in...

Page 281: ...ITT calculation follow this procedure 1 Write high byte of initial seed value to CRCH 2 Write low byte of initial seed value to CRCL 3 Write first byte of data on which CRC is to be calculated to CRCL...

Page 282: ...Cyclic Redundancy Check Generator S08CRCV2 MC9S08JS16 MCU Series Reference Manual Rev 4 282 Freescale Semiconductor...

Page 283: ...features such as CPU register modify breakpoints and single instruction trace commands In the HCS08 family address and data bus signals are not available on external pins not even in test mode Debug i...

Page 284: ...of flow addresses or Event only data Two types of breakpoints Tag breakpoints for instruction opcodes Force breakpoints for any address access Nine trigger modes Basic A only A OR B Sequence A then B...

Page 285: ...he running application program Figure 17 1 BDM Tool Connector 17 2 1 BKGD Pin Description BKGD is the single wire background debug interface pin The primary function of this pin is for bidirectional s...

Page 286: ...cur between falling edges from the host Any BDC command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU system The custom seri...

Page 287: ...ved start of the bit time in the target MCU The host holds the BKGD pin low long enough for the target to recognize it at least two target BDC cycles The host must release the low drive before the tar...

Page 288: ...it time as perceived by the target MCU The host initiates the bit time but the target HCS08 finishes it Because the target wants the host to receive a logic 0 it drives the BKGD pin low for 13 BDC clo...

Page 289: ...ctive background mode while non intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program Table 17 1 shows all HCS08 BDC co...

Page 290: ...read data in the target to host direction WD 8 bits of write data in the host to target direction RD16 16 bits of read data in the target to host direction WD16 16 bits of write data in the host to t...

Page 291: ...intrusive E2 RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non intrusive C2 WBKP Write BDCBKPT breakpoint register GO Active BDM 08 d Go to execute the user application program starting at the addr...

Page 292: ...e host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent 17 2 4 BDC Hardw...

Page 293: ...to only being read from memory into the instruction queue The comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes Comparators are disable...

Page 294: ...by reading DBGFH then DBGFL at regular periodic intervals The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO Additional perio...

Page 295: ...before triggering FIFO actions The BEGIN bit in DBGT chooses whether the FIFO begins storing data when the qualified trigger is detected begin trace or the FIFO stores data in a circular fashion from...

Page 296: ...B and R W must match RWA if RWAEN 1 All three conditions must be met within the same bus cycle to cause a trigger In full trigger modes it is not useful to specify a tag type CPU breakpoint BRKEN TAG...

Page 297: ...ry in the device overview chapter of this data sheet for the absolute address assignments for all DBG registers This section refers to registers and control bits only by their names A Freescale provid...

Page 298: ...mode commands 6 BDMACT Background Mode Active Status This is a read only status bit 0 BDM not active user application program running 1 BDM active and waiting for serial commands 5 BKPTEN BDC Breakpoi...

Page 299: ...stop and into active background mode where all BDC commands work Whenever the host forces the target MCU into active background mode the host must issue a READ_STATUS command to check that BDMACT 1 be...

Page 300: ...pare value bits for the low order eight bits of comparator A This register is forced to 0x00 at reset and can be read at any time or written at any time unless ARM 1 17 4 3 3 Debug Comparator B High R...

Page 301: ...IFO high order half of each FIFO word is unused When reading 8 bit words out of the FIFO simply read DBGFL repeatedly to get successive bytes of data from the FIFO It isn t necessary to read DBGFH in...

Page 302: ...can cause information to be stored in the FIFO without generating a break request to the CPU For an end trace CPU break requests are issued to the CPU when the comparator s and R W meet the trigger r...

Page 303: ...ugh the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match address is actually executed 0 Trigger on access to compare address force 1 Trigger if...

Page 304: ...M control bit in DBGC while DBGEN 1 and is automatically cleared at the end of a debug run A debug run is completed when the FIFO is full begin trace or when a trigger event is detected end trace A de...

Page 305: ......

Page 306: ...ion in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee rega...

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