Freescale Semiconductor HCS08 Series, Reference Manual

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Chapter 6 Parallel Input/Output
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 81
6.3.1 Internal Pullup Enable
An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the
pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral function regardless of the state of the corresponding
pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
6.3.2 Output Slew Rate Control Enable
Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate
control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in
order to reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
6.3.3 Output Drive Strength Select
An output pin can be selected to have high output drive strength by setting the corresponding bit in one of
the drive strength select registers (PTxDSn). When high drive is selected, the pin is capable of sourcing
and sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure
that the total current source and sink limits for the chip are not exceeded. Drive strength selection is
intended to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive
allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller
load. Because of this, the EMC emissions may be affected by enabling pins as high drive.
6.4 Pin Behavior in Stop Modes
Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An
explanation of I/O behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed. CPU register status and the state of I/O registers must
be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon
recovery from stop2 mode, before accessing any I/O, the user must examine the state of the PPDF
bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power-on reset had
occurred. If the PPDF bit is 1, I/O register states must be restored from the values saved in RAM
before the STOP instruction was executed. Peripherals may require initialization or restoration to
their pre-stop condition. The user must then write a 1 to the PPDACK bit in the SPMSC2 register.
Access to I/O is now permitted again in the user’s application program.
• In stop3 mode, all I/O is maintained because internal logic circuitry stays powered up. Upon
recovery, normal I/O function is available to the user.
6.5 Parallel I/O and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports and pin control
functions. These parallel I/O registers are located in page zero of the memory map and the pin control
registers are located in the high-page register section of memory.