Freescale Semiconductor HCS08 Series, Reference Manual

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Chapter 5 Resets, Interrupts, and System Configuration
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 77
5.7.9 System Power Management Status and Control 1 Register
(SPMSC1)
This high-page register contains status and control bits to support the low-voltage detect function. This
register must be written during the user’s reset initialization program to set the desired controls even if the
desired settings are the same as the reset settings.
R LVWF
1
0
LVWIE LVDRE
2
LVDSE LVDE
2
0 0
W LVWACK
Reset: 0 0 0 1 1 1 0 0
= Unimplemented or Reserved
1
LVWF will be set in the case when V
Supply
transitions below the trip point or after reset and V
Supply
is already below V
LVW
.
2
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-11. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-12. SPMSC1 Register Field Descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag — The LVWF bit indicates the low-voltage warning status.
0 low-voltage warning is not present.
1 low-voltage warning is present or was present.
6
LVWACK
Low-Voltage Warning Acknowledge — If LVWF = 1, a low-voltage condition has occurred. To acknowledge this
low-voltage warning, write 1 to LVWACK, which will automatically clear LVWF to 0 if the low-voltage warning is
no longer present.
5
LVWIE
Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF = 1
4
LVDRE
Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset
(provided LVDE = 1).
0 LVD events do not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.