Freescale Semiconductor HCS08 Series, Reference Manual

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16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
210 Freescale Semiconductor
13.4.10.3 SPTEF
SPTEF occurs when the SPI transmit buffer is ready to accept new data. In 8-bit mode, SPTEF is set only
after all 8 bits have been moved from SPIDL into the shifter. In 16-bit mode, SPTEF is set only after all
16 bits have been moved from SPIDH:SPIDL into the shifter.
Once SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process which is
described in
Section 13.3.4, “SPI Status Register (SPIS) .
13.4.10.4 SPMF
SPMF occurs when the data in the receive data buffer is equal to the data in the SPI match register. In 8-bit
mode, SPMF is set only after bits 8–0 in the receive data buffer are determined to be equivalent to the value
in SPIML. In 16-bit mode, SPMF is set after bits 15–0 in the receive data buffer are determined to be
equivalent to the value in SPIMH:SPIML.
13.5 Initialization/Application Information
13.5.1 SPI Module Initialization Example
13.5.1.1 Initialization Sequence
Before the SPI module can be used for communication, an initialization procedure must be carried out, as
follows:
1. Update control register 1 (SPIC1) to enable the SPI and to control interrupt enables. This register
also sets the SPI as master or slave, determines clock phase and polarity, and configures the main
SPI options.
2. Update control register 2 (SPIC2) to enable additional SPI functions such as the SPI match
interrupt feature, the master mode-fault function, and bidirectional mode output. 8- or 16-bit mode
select and other optional features are controlled here as well.
3. Update the baud rate register (SPIBR) to set the prescaler and bit rate divisor for an SPI master.
4. Update the hardware match register (SPIMH:SPIML) with the value to be compared to the receive
data register for triggering an interrupt if hardware match interrupts are enabled.
5. In the master, read SPIS while SPTEF = 1, and then write to the transmit data register
(SPIDH:SPIDL) to begin transfer.
13.5.1.2 Pseudo—Code Example
In this example, the SPI module will be set up for master mode with only hardware match interrupts
enabled. The SPI will run in 16-bit mode at a maximum baud rate of bus clock divided by 2. Clock phase
and polarity will be set for an active-high SPI clock where the first edge on SPSCK occurs at the start of
the first cycle of a data transfer.