Freescale Semiconductor HCS08 Series, Reference Manual

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Chapter 3 Modes of Operation
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 31
3.6 Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set. In
any stop mode, the bus and CPU clocks are halted. The MCG module can be configured to leave the
reference clocks running. See
Chapter 9, “Multi-Purpose Clock Generator (S08MCGV1) ,” for more
information.
Some HCS08 devices that are designed for low-voltage operation (1.8 to 3.6 V) also include stop1 mode.
The MC9S08JS16 series of MCUs do not include stop1 mode.
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
3.6.1 Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions shown in Table 3-1 . The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
clock (RTC) interrupt, the USB resume interrupt, LVD, IRQ, KBI, or the SCI.
If stop3 is exited by the RESET pin, then the MCU is reset and operation will resume after taking the reset
vector. Exit by one of the internal interrupt sources results in the MCU taking the appropriate interrupt
vector.
3.6.1.1 LVD Enabled in Stop Mode
The LVD system is capable of generating an interrupt or a reset when the supply voltage drops below the
LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the
CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user
attempts to enter stop2 with the LVD enabled for stop, the MCU will enter stop3 instead.
Table 3-1. Stop Mode Selection
STOPE ENBDM
1
1
ENBDM is located in the BDCSCR which is only accessible through BDC commands, see Section 14.4.1.1,
“BDC Status and Control Register (BDCSCR) .”
LVDE LVDSE PPDC Stop Mode
0 x x x Stop modes disabled; illegal opcode reset if STOP
instruction executed
1 1 x x Stop3 with BDM enabled
2
2
When in stop3 mode with BDM enabled, The S
IDD
will be near R
IDD
levels because internal clocks are
enabled.
1 0 Both bits must be 1 x Stop3 with voltage regulator active
1 0 Either bit a 0 0 Stop3
1 0 Either bit a 0 1 Stop2