SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2
2.12 Watchdog Control Signals
The simplest way to implement the watchdog timer is to utilize the
AM335X
internal
WDT
function. This function is available to users through the standard
Linux Watchdog API. The Watchdog can be initialized and controlled by the
API (Application Program Interface) called Embedded Application Software
Interface (
EASI
). For more details about
EASI
, refer to the
EASI
Programmers
Guide or following the link below:
http://www.kernel.org/doc/Documentation/watchdog/watchdog-api.txt.
The internal WDT is a 32 bit counter that resets the processor only when it rolls
over to zero. The processor can reset the counter or turn it off, but, correctly
used, it will reset the processor in case of a code crash. To avoid getting reset,
the program must reset the timer every so often.
In addition to the software trigger available via
EASI
, the Watchdog on a
SMARC
module can be hardware-triggered by an external control circuitry. A
watchdog timer output signal,
WDT_TIME_OUT#,
is defined on SMARC
specification.
If the Watchdog timer has expired without a software or hardware trigger
occurrence, the SMARC module will signal this with a low level output on the
'
WDT_TIME_OUT
#' (Watchdog event indicator) signal and trigger the reset
event.
SMARC Edge Finger
I/O
Type
Power
Rail
Description
Pin#
Pin
Name
S145
WDT_TIME_OUT#
O
CMOS
3.3V
Watchdog Timer Output
2.12.1. External WDT Control Circuitry Reference Schematic
Figure below is the reference schematic of external WDT control circuit.
Instead of reset the processor only, the external WDT circuitry will trigger the
hardware reset.