Compsee Apex III, Technical Reference Manual

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Apex PDT Technical Reference Manual 4 BIOS
COAM30002 Rev. 2.00 8/13/02
4-10
Code Beeps POST Routine Description
000h Reset
002h Verify Real Mode
004h Get CPU type
006h Initialize system hardware
008h Initialize chipset registers with initial POST values
009h Set in POST flag
00Ah Initialize CPU registers
00Bh Enable CPU cache
00Ch Initialize caches to initial POST values
00Eh Initialize I/O
00Fh Initialize the local bus IDE
010h Initialize Power Management
011h Load alternate registers with initial POST values
012h Restore CPU control word during warm boot
014h Initialize keyboard controller
016h 1-2-2-3 BIOS ROM checksum
017h Autosize the RAM
018h 8254 timer initialization
01Ah 8237 DMA controller initialization
01Ch Reset Programmable Interrupt Controller
020h 1-3-1-1 Test DRAM refresh
022h 1-3-1-3 Test 8742 Keyboard Controller
024h Set ES segment register to 4 GB
028h Autosize DRAM
02Ah Clear 512K base RAM
02Ch 1-3-4-1 RAM failure on address line xxxx
02Eh 1-3-4-3 RAM failure on data bits xxxx of low byte of
memory bus
02Fh Shadow the BIOS
030h 1-4-1-1 RAM failure on data bits xxxx of high byte of
memory bus
034h Test CMOS RAM
036h Warm start shut down
038h Shadow the system BIOS RAM
03Ah Autosize cache
03Ch Configure advanced chipset registers
03Dh Load alternate registers with CMOS values
042h Initialize interrupt vectors
044h Initialize BIOS interrupts
046h 2-1-2-3 Check ROM copyright notice
048h Check video configuration against CMOS
Table 4-2: BIOS Test Point And Beep Code Information