MC96F6432
June 22, 2018 Ver. 2.9
281
LCDCCR (LCD Driver Contrast Control Low Register) : 9BH
7
6
5
4
3
2
1
0
LCTEN
–
–
–
VLCD3
VLCD
VLCD1
VLCD0
R/W
–
–
–
R/W
R/W
R/W
R/W
Initial value : 00H
LCTEN
Control LCD Driver Contrast
0
LCD Driver Contrast disable
1
LCD Driver Contrast enable
VLCD[3:0]
VLC0 Voltage Control when the contrast is enabled
VLCD3 VLCD 2
VLCD 1
VLCD 0
Description
0
0
0
0
VLC0 = VDD x 16/31 step
0
0
0
1
VLC0 = VDD x 16/30 step
0
0
1
0
VLC0 = VDD x 16/29 step
0
0
1
1
VLC0 = VDD x 16/28 step
0
1
0
0
VLC0 = VDD x 16/27 step
0
1
0
1
VLC0 = VDD x 16/26 step
0
1
1
0
VLC0 = VDD x 16/25 step
0
1
1
1
VLC0 = VDD x 16/24 step
1
0
0
0
VLC0 = VDD x 16/23 step
1
0
0
1
VLC0 = VDD x 16/22 step
1
0
1
0
VLC0 = VDD x 16/21 step
1
0
1
1
VLC0 = VDD x 16/20 step
1
1
0
0
VLC0 = VDD x 16/19 step
1
1
0
1
VLC0 = VDD x 16/18 step
1
1
1
0
VLC0 = VDD x 16/17 step
1
1
1
1
VLC0 = VDD x 16/16 step
NOTES) The LCD contrast step is based on 1/4 bias.
1/4 bias : VDD x (16/31
– VLC[3:0])
1/3 bias : VDD x (12/27
– VLC[3:0])
1/2 bias : VDD x (8/23
– VLC[3:0])
Summary of Contents for MC96F6332D
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...