MC96F6432
118
June 22, 2018 Ver. 2.9
11.3.6 Register Description for Watch Dog Timer
WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH
7
6
5
4
3
2
1
0
WDTCNT 7
WDTCNT 6
WDTCNT 5
WDTCNT 4
WDTCNT3
WDTCNT 2
WDTCNT 1
WDTCNT 0
R
R
R
R
R
R
R
R
Initial value : 00H
WDTCNT[7:0]
WDT Counter
WDTDR (Watch Dog Timer Data Register: Write Case) : 8EH
7
6
5
4
3
2
1
0
WDTDR7
WDTDR 6
WDTDR 5
WDTDR 4
WDTDR 3
WDTDR 2
WDTDR 1
WDTDR 0
W
W
W
W
W
W
W
W
Initial value : FFH
WDTDR[7:0]
Set a period
WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1)
NOTE) Do not write
“0” in the WDTDR register.
WDTCR (Watch Dog Timer Control Register) : 8DH
7
6
5
4
3
2
1
0
WDTEN
WDTRSON
WDTCL
–
–
–
WDTCK
WDTIFR
R/W
R/W
R/W
–
–
–
R/W
R/W
Initial value : 00H
WDTEN
Control WDT Operation
0
Disable
1
Enable
WDTRSON
Control WDT RESET Operation
0
Free Running 8-bit timer
1
Watch Dog Timer RESET ON
WDTCL
Clear WDT Counter
0
Free Run
1
Clear WDT Counter (auto clear after 1 Cycle)
WDTCK
Control WDT Clock Selection Bit
0
BIT overflow for WDT clock (WDTRC disable)
1
WDTRC for WDT clock (WDTRC enable)
WDTIFR
When WDT Interrupt occurs, this bit becomes
‘1’. For clearing bit, write
‘0’ to this bit or auto clear by INT_ACK signal. Writing “1” has no effect.
0
WDT Interrupt no generation
1
WDT Interrupt generation
Summary of Contents for MC96F6332D
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
