MC96F6432
150
June 22, 2018 Ver. 2.9
T2CRH (Timer 2 Control High Register) : C3H
7
6
5
4
3
2
1
0
T2EN
–
T2MS1
T2MS0
–
–
–
T2CC
R/W
–
R/W
R/W
–
–
–
R/W
Initial value : 00H
T2EN
Control Timer 2
0
Timer 2 disable
1
Timer 2 enable (Counter clear and start)
T2MS[1:0]
Control Timer 2 Operation Mode
T2MS1 T2MS0 Description
0
0
Timer/counter mode (T2O: toggle at A match)
0
1
Capture mode (The A match interrupt can occur)
1
0
PPG one-shot mode (PWM2O)
1
1
PPG repeat mode (PWM2O)
T2CC
Clear Timer 2 Counter
0
No effect
1
Clear the Timer 2 counter (When write, automatically
cleared “0” after being cleared counter)
Summary of Contents for MC96F6332D
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
