Abov MC96F6332D, User Manual

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MC96F6432
268 June 22, 2018 Ver. 2.9
USI1ST2 (USI1 Status Register 2: For I2C mode) : F2H
7 6 5 4 3 2 1 0
GCALL1 TEND1 STOPD1 SSEL1 MLOST1 BUSY1 TMODE1 RXACK1
R/W R/W R/W R/W R/W R/W R R/W
Initial value : 00H
GCALL1
(NOTE)
This bit has different meaning depending on whether I2C is master or
slave. When I2C is a master, this bit represents whether it received
AACK (address ACK) from slave.
0 No AACK is received (Master mode)
1 AACK is received (Master mode)
When I2C is a slave, this bit is used to indicated general call.
0 General call address is not detected (Slave mode)
1 General call address is detected (Slave mode)
TEND1
(NOTE)
This bit is set when 1-byte of data is transferred completely
0 1 byte of data is not completely transferred
1 1 byte of data is completely transferred
STOPD1
(NOTE)
This bit is set when a STOP condition is detected.
0 No STOP condition is detected
1 STOP condition is detected
SSEL1
(NOTE)
This bit is set when I2C is addressed by other master.
0 I2C is not selected as a slave
1 I2C is addressed by other master and acts as a slave
MLOST1
(NOTE)
This bit represents the result of bus arbitration in master mode.
0 I2C maintains bus mastership
1 I2C maintains bus mastership during arbitration process
BUSY1
This bit reflects bus status.
0 I2C bus is idle, so a master can issue a START condition
1 I2C bus is busy
TMODE1 This bit is used to indicate whether I2C is transmitter or receiver.
0 I2C is a receiver
1 I2C is a transmitter
RXACK1 This bit shows the state of ACK signal
0 No ACK is received
1 ACK is received at ninth SCL period
NOTE)
1. The GCALL1, TEND1, STOPD1, SSEL1, and MLOST1 bits can be source
of interrupt.
2. When an I2C interrupt occurs except for STOP mode, the SCL1 line is hold
LOW. To release SCL1, Clear to
“0b” all interrupt source bits in USI1ST2
register.
3. The GCALL1, TEND1, STOPD1, SSEL1, MLOST1, and RXACK1 bits are
cleared when
“0b” is written to the corresponding bit.