Abov MC96F6332D, User Manual

Page: 243 / 327

MC96F6432
June 22, 2018 Ver. 2.9 243
11.13.11 USI1 SPI Mode
The USI1 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following
features.
- Full Duplex, Three-wire synchronous data transfer
- Mater and Slave Operation
- Supports all four SPI0 modes of operation (mode 0, 1, 2, and 3)
- Selectable LSB first or MSB first data transfer
- Double buffered transmit and receive
- Programmable transmit bit rate
When SPI mode is enabled (USI1MS[1:0]=
”11”), the slave select (SS1) pin becomes active LOW input in slave
mode operation, or can be output in master mode operation if USI1SSEN bit is set to
‘0’.
Note that during SPI mode of operation, the pin RXD1 is renamed as MISO1 and TXD1 is renamed as MOSI1
for compatibility to other SPI devices.
11.13.12 USI1 SPI Clock Formats and Timing
To accommodate a wide variety if synchronous serial peripherals from different manufacturers, the USI1 has a
clock polarity bit (CPOL1) and a clock phase control bit (CPHA1) to select one of four clock formats for data
transfers. CPOL1 selectively insert an inverter in series with the clock. CPHA1 chooses between two different
clock phase relationships between the clock and data. Note that CPHA1 and CPOL1 bits in USI1CR1 register
have different meanings according to the USI1MS[1:0] bits which decides the operating mode of USI1.
Table below shows four combinations of CPOL1 and CPHA1 for SPI mode 0, 1, 2, and 3.
Table 11-23 CPOL1 Functionality
SPI Mode CPOL1 CPHA1 Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
1 0 1 Setup (Rising) Sample (Falling)
2 1 0 Sample (Falling) Setup (Rising)
3 1 1 Setup (Falling) Sample (Rising)