Abov MC96F6332D, User Manual

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MC96F6432
250 June 22, 2018 Ver. 2.9
Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1)
Figure 11.93 Arbitration Procedure of Two Masters (USI1)
11.13.20 USI1 I2C Operation
The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a
transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry
on other operations during a I2C byte transfer.
Note that when a I2C interrupt is generated, IIC1IFR flag in USI1CR4 register is set, it is cleared when all
interrupt source bits in the USI1ST2
register are cleared to “0b”.
When I2C interrupt occurs, the SCL1 line is hold
LOW until clearing
“0b” all interrupt source bits in USI1ST2 register. When the IIC1IFR flag is set, the USI1ST2
contains a value indicating the current state of the I2C bus. According to the value in USI1ST2, software can
decide what to do next.
I2C can operate in 4 modes by configuring master/slave, transmitter/receiver. The operating mode is
configured by a winning master. A more detailed explanation follows below.
11.13.20.1 USI1 I2C Master Transmitter
To operate I2C in master transmitter, follow the recommended steps below.
1. Enable I2C by setting USI1MS[1:0] bits in USI1CR1 and USI1EN bit in USI1CR2. This provides main
clock to the peripheral.
Device1
DataOut
SCL1 on BUS
Device2
DataOut
SDA1 on BUS
S
Arbitration Process
not adaped
Device 1 loses
Arbitration
Device1 outputs
High
High Counter
Reset
Fast Device
SCLOUT
Slow Device
SCLOUT
SCL1
Wait High
Counting
Start High
Counting