Abov MC96F6332D, User Manual

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MC96F6432
96 June 22, 2018 Ver. 2.9
10.4 Interrupt Vector Table
The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served,
long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests
have their own priority order.
Table 10-2 Interrupt Vector Address Table
Interrupt Source Symbol
Interrupt
Enable Bit
Priority Mask Vector Address
Hardware Reset RESETB 0 0 0 Non-Maskable 0000H
External Interrupt 10 INT0 IE.0 1 Maskable 0003H
External Interrupt 11 INT1 IE.1 2 Maskable 000BH
USI1 I2C Interrupt INT2 IE.2 3 Maskable 0013H
USI1 Rx Interrupt INT3 IE.3 4 Maskable 001BH
USI1 Tx Interrupt INT4 IE.4 5 Maskable 0023H
External Interrupt 0 - 7 INT5 IE.5 6 Maskable 002BH
External Interrupt 8 INT6 IE1.0 7 Maskable 0033H
- INT7 IE1.1 8 Maskable 003BH
USI0 I2C Interrupt INT8 IE1.2 9 Maskable 0043H
USI0 Rx Interrupt INT9 IE1.3 10 Maskable 004BH
USI0 Tx Interrupt INT10 IE1.4 11 Maskable 0053H
External Interrupt 12 INT11 IE1.5 12 Maskable 005BH
T0 Overflow Interrupt INT12 IE2.0 13 Maskable 0063H
T0 Match Interrupt INT13 IE2.1 14 Maskable 006BH
T1 Match Interrupt INT14 IE2.2 15 Maskable 0073H
T2 Match Interrupt INT15 IE2.3 16 Maskable 007BH
T3 Match Interrupt INT16 IE2.4 17 Maskable 0083H
T4 Interrupt INT17 IE2.5 18 Maskable 008BH
ADC Interrupt INT18 IE3.0 19 Maskable 0093H
SPI 2 Interrupt INT19 IE3.1 20 Maskable 009BH
WT Interrupt INT20 IE3.2 21 Maskable 00A3H
WDT Interrupt INT21 IE3.3 22 Maskable 00ABH
BIT Interrupt INT22 IE3.4 23 Maskable 00B3H
- INT23 IE3.5 24 Maskable 00BBH
For maskable
interrupt execution, EA bit must set ‘1’ and specific interrupt must be enabled by writing ‘1’ to
associated bit in the IEx. If an interrupt request is received, the specific interrupt request flag is set to
‘1’. And it
remains ‘1’ until CPU accepts interrupt. If the interrupt is served, the interrupt request flag will be cleared
automatically.
10.5 Interrupt Sequence
An interrupt request is held
until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an
instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the
current instruction, CPU executes internally LCALL instruction and saves the PC at stack. For the interrupt
service routine, the interrupt controller gives the address of LJMP instruction to CPU. Since the end of the
execution of current instruction, it needs 3~9 machine cycles to go to the interrupt service routine. The interrupt
service task is terminated by the interrupt return instruction [RETI]. Once an interrupt request is generated, the
following process is performed.