MC96F6432
108
June 22, 2018 Ver. 2.9
EIFLAG0 (External Interrupt Flag 0 Register) : C0H
7
6
5
4
3
2
1
0
FLAG7
FLAG6
FLAG5
FLAG4
FLAG3
FLAG2
FLAG1
FLAG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
EIFLAG0[7:0]
When an External Interrupt 0-7 is occurred, the flag becomes
‘1’.
The flag is cleared only by writing
‘0’ to the bit. So, the flag should
be cleared by software. Writing
“1” has no effect.
0
External Interrupt 0 ~ 7 not occurred
1
External Interrupt 0 ~ 7 occurred
Note) Do not use the
“direct bit test and branch” instruction for input port, more detail information is at
Appendix B.
Example) Avoid direct input port bit test and branch condition as below
If(FLAG0)
→
if(EIFLAG0 & 0x01)
EIPOL0H (External Interrupt Polarity 0 High Register): A5H
7
6
5
4
3
2
1
0
POL7
POL6
POL5
POL4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
EIPOL0H[7:0]
External interrupt (EINT7, EINT6, EINT5, EINT4) polarity selection
POLn[1:0]
Description
0
0
No interrupt at any edge
0
1
Interrupt on rising edge
1
0
Interrupt on falling edge
1
1
Interrupt on both of rising and falling edge
Where n =4, 5, 6 and 7
EIPOL0L (External Interrupt Polarity 0 Low Register): A4H
7
6
5
4
3
2
1
0
POL3
POL2
POL1
POL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
EIPOL0L[7:0]
External interrupt (EINT0, EINT1, EINT2, EINT3) polarity selection
POLn[1:0]
Description
0
0
No interrupt at any edge
0
1
Interrupt on rising edge
1
0
Interrupt on falling edge
1
1
Interrupt on both of rising and falling edge
Where n =0, 1, 2 and 3
Summary of Contents for MC96F6332D
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
