MC96F6432
June 22, 2018 Ver. 2.9
139
T1CRH (Timer 1 Control High Register) : BBH
7
6
5
4
3
2
1
0
T1EN
–
T1MS1
T1MS0
–
–
–
T1CC
R/W
–
R/W
R/W
–
–
–
R/W
Initial value : 00H
T1EN
Control Timer 1
0
Timer 1 disable
1
Timer 1 enable (Counter clear and start)
T1MS[1:0]
Control Timer 1 Operation Mode
T1MS1 T1MS0 Description
0
0
Timer/counter mode (T1O: toggle at A match)
0
1
Capture mode (The A match interrupt can occur)
1
0
PPG one-shot mode (PWM1O)
1
1
PPG repeat mode (PWM1O)
T1CC
Clear Timer 1 Counter
0
No effect
1
Clear the Timer 1 counter (When write, automatically
cleared “0” after being cleared counter)
Summary of Contents for MC96F6332D
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
