Abov MC96F6332D, User Manual

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MC96F6432
228 June 22, 2018 Ver. 2.9
USI0CR3 (USI0 Control Register 3: For UART, SPI, and I2C mode) : DBH
7 6 5 4 3 2 1 0
MASTER0 LOOPS0 DISSCK0 USI0SSEN FXCH0 USI0SB USI0TX8 USI0RX8
R/W R/W R/W R/W R/W R/W R/W R
Initial value : 00H
MASTER0 Selects master or slave in SPI and synchronous mode operation and
controls the direction of SCK0 pin
0 Slave mode operation (External clock for SCK0).
1 Master mode operation(Internal clock for SCK0).
LOOPS0 Controls the loop back mode of USI0 for test mode (only UART and SPI
mode)
0 Normal operation
1 Loop Back mode
DISSCK0 In synchronous mode of operation, selects the waveform of SCK0 output
0 ACK is free-running while UART is enabled in synchronous
master mode
1 ACK is active while any frame is on transferring
USI0SSEN This bit controls the SS0 pin operation (only SPI mode)
0 Disable
1 Enable (The SS0 pin should be a normal input)
FXCH0 SPI port function exchange control bit (only SPI mode)
0 No effect
1 Exchange MOSI0 and MISO0 function
USI0SB
Selects the length of stop bit in asynchronous or synchronous mode of
operation.
0 1 Stop Bit
1 2 Stop Bit
USI0TX8
The ninth bit of data frame in asynchronous or synchronous mode of
operation. Write this bit first before loading the USI0DR register
0 MSB (9
th
bit) to be transmitted is
‘0’
1 MSB (9
th
bit) to be transmitted is
‘1’
USI0RX8 The ninth bit of data frame in asynchronous or synchronous mode of
operation. Read this bit first before reading the receive buffer (only UART
mode).
0 MSB (9
th
bit) received is
‘0’
1 MSB (9
th
bit) received is
‘1’