Abov MC96F6332D, User Manual

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MC96F6432
June 22, 2018 Ver. 2.9 115
BITCR (Basic Interval Timer Control Register) : 8BH
7 6 5 4 3 2 1 0
BITIFR BITCK1 BITCK0
–
BCLR BCK2 BCK1 BCK0
R/W R/W R/W
–
R/W R/W R/W R/W
Initial value : 01H
BITIFR When BIT Interrupt occurs, this bit becomes
‘1’. For clearing bit, write ‘0’
to this bit or auto clear by INT_ACK signal. Writing
“1” has no effect.
0 BIT interrupt no generation
1 BIT interrupt generation
BITCK[1:0] Select BIT clock source
BITCK1 BITCK0 Description
0 0 fx/4096
0 1 fx/1024
1 0 fx/128
1 1 fx/16
BCLR
If this bit is written to
‘1’, BIT Counter is cleared to ‘0’
0 Free Running
1 Clear Counter
BCK[2:0] Select BIT overflow period
BCK2 BCK1 BCK0 Description
0 0 0 Bit 0 overflow (BIT Clock * 2)
0 0 1 Bit 1 overflow (BIT Clock * 4) (default)
0 1 0 Bit 2 overflow (BIT Clock * 8)
0 1 1 Bit 3 overflow (BIT Clock * 16)
1 0 0 Bit 4 overflow (BIT Clock * 32)
1 0 1 Bit 5 overflow (BIT Clock * 64)
1 1 0 Bit 6 overflow (BIT Clock * 128)
1 1 1 Bit 7 overflow (BIT Clock * 256)