Abov MC96F6332D, User Manual

Page: 260 / 327

MC96F6432
260 June 22, 2018 Ver. 2.9
11.13.22 Register Map
Table 11-24 USI1 Register Map
Name Address Dir Default Description
USI1BD F3H R/W FFH USI1 Baud Rate Generation Register
USI1DR F5H R/W 00H USI1 Data Register
USI1SDHR F4H R/W 01H USI1 SDA Hold Time Register
USI1SCHR F7H R/W 3FH USI1 SCL High Period Register
USI1SCLR F6H R/W 3FH USI1 SCL Low Period Register
USI1SAR EDH R/W 00H USI1 Slave Address Register
USI1CR1 E9H R/W 00H USI1 Control Register 1
USI1CR2 EAH R/W 00H USI1 Control Register 2
USI1CR3 EBH R/W 00H USI1 Control Register 3
USI1CR4 ECH R/W 00H USI1 Control Register 4
USI1ST1 F1H R/W 80H USI1 Status Register 1
USI1ST2 F2H R 00H USI1 Status Register 2
11.13.23 USI1 Register Description
USI1 module consists of USI1 baud rate generation register (USI1BD), USI1 data register (USI1DR), USI1 SDA
hold time register (USI1SDHR), USI1 SCL high period register (USI1SCHR), USI1 SCL low period Register
(USI1SCLR), USI1 slave address register (USI1SAR), USI1 control register 1/2/3/4 (USI1CR1/2/3/4), USI1
status register 1/2 (USI1ST1/2).
11.13.24 Register Description for USI1
USI1BD (USI1 Baud- Rate Generation Register: For UART and SPI mode) : F3H
7 6 5 4 3 2 1 0
USI1BD7 USI1BD 6 USI1BD 5 USI1BD 4 USI1BD 3 USI1BD 2 USI1BD 1 USI1BD 0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
USI1BD[7:0]
The value in this register is used to generate internal baud rate in
asynchronous mode or to generate SCK1 clock in SPI mode. To
prevent malfunction, do not write
‘0’ in asynchronous mode and do
not write
‘0’ or ‘1’ in SPI mode.
NOTE) In common with USI1SAR register, USI1BD register is
used for slave address register when the USI1 I2C mode.