MC96F6432
June 22, 2018 Ver. 2.9
75
P0OD (P0 Open-drain Selection Register) : 91H
7
6
5
4
3
2
1
0
P07OD
P06OD
P05OD
P04OD
P03OD
P02OD
P01OD
P00OD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
P0OD[7:0]
Configure Open-drain of P0 Port
0
Push-pull output
1
Open-drain output
P0DB (P0 Debounce Enable Register) : DEH
7
6
5
4
3
2
1
0
DBCLK1
DBCLK0
P07DB
P06DB
P05DB
P04DB
P03DB
P02DB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
DBCLK[1:0]
Configure Debounce Clock of Port
DBCLK1 DBCLK0 Description
0
0
fx/1
0
1
fx/4
1
0
fx/4096
1
1
Reserved
P07DB
Configure Debounce of P07 Port
0
Disable
1
Enable
P06DB
Configure Debounce of P06 Port
0
Disable
1
Enable
P05DB
Configure Debounce of P05 Port
0
Disable
1
Enable
P04DB
Configure Debounce of P04 Port
0
Disable
1
Enable
P03DB
Configure Debounce of P03Port
0
Disable
1
Enable
P02DB
Configure Debounce of P02 Port
0
Disable
1
Enable
NOTES) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the
signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid
edge.
3. The port debounce is automatically disabled at stop mode and recovered after stop mode release.
Summary of Contents for MC96F6332D
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
