MC96F6432
June 22, 2018 Ver. 2.9
297
14. On-chip Debug System
14.1 Overview
14.1.1 Description
On-chip debug system (OCD) of MC96F6432 can be used for programming the non-volatile memories and on-
chip debugging. Detail descriptions for programming via the OCD interface can be found in the following chapter.
Figure 14.1 shows a block diagram of the OCD interface and the On-chip Debug system.
14.1.2 Feature
•
Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus
•
Debugger Access to:
−
All Internal Peripheral Units
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Internal data RAM
−
Program Counter
−
Flash and Data EEPROM Memories
•
Extensive On-chip Debug Support for Break Conditions, Including
−
Break Instruction
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Single Step Break
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Program Memory Break Points on Single Address
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Programming of Flash, EEPROM, Fuses, and Lock Bits through the two-wire Interface
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On-chip Debugging Supported by Dr.Choice
®
•
Operating frequency
Supports the maximum frequency of the target MCU
Figure 14.1 Block Diagram of On-Chip Debug System
BDC
Format
converter
USB
CPU
Code memory
-
SRAM
-
Flash
-
EEPROM
Data memory
DBG Register
Peripheral
User I/O
Address bus
Internal data bus
DSDA
DSCL
Target MCU internal circuit
DBG
Control
Summary of Contents for MC96F6332D
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
