Abov MC96F6332D, User Manual

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MC96F6432
June 22, 2018 Ver. 2.9 229
USI0CR4 (USI0 Control Register 4: For I2C mode) : DCH
7 6 5 4 3 2 1 0
IIC0IFR
–
TXDLYENB0 IIC0IE ACK0EN IMASTER0 STOPC0 STARTC0
R
–
R/W R/W R/W R R/W R/W
Initial value : 00H
IIC0IFR This is an interrupt flag bit for I2C mode. When an interrupt occurs, this
bit becomes
‘1’. This bit is cleared when all interrupt source bits in the
USI0ST2 register are cleared to
“0b”. Writing “1” has no effect.
0 I2C interrupt no generation
1 I2C interrupt generation
TXDLYENB0 USI0SDHR register control bit
0 Enable USI0SDHR register
1 Disable USI0SDHR register
IIC0IE Interrupt Enable bit for I2C mode
0 Interrupt from I2C is inhibited (use polling)
1 Enable interrupt for I2C
ACK0EN Controls ACK signal Generation at ninth SCL0 period.
0 No ACK signal is generated (SDA0 =1)
1 ACK signal is generated (SDA0 =0)
NOTES) ACK signal is output (SDA =0) for the following 3 cases.
1. When received address packet equals to USI0SLA bits in USI0SAR.
2. When received address packet equals to value 0x00 with GCALL0
enabled.
3. When I2C operates as a receiver (master or slave)
IMASTER0 Represent operating mode of I2C
0 I2C is in slave mode
1 I2C is in master mode
STOPC0
When I2C is master, STOP condition generation
0 No effect
1 STOP condition is to be generated
STARTC0 When I2C is master, START condition generation
0 No effect
1 START or repeated START condition is to be generated