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NUC126
Aug. 08, 2018
Page
489
of 943
Rev 1.03
NUC12
6 S
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NCE
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NUA
L
PWM Interrupt Flag Register 1 (PWM_INTSTS1)
Register
Offset
R/W
Description
Reset Value
PWM_INTSTS
1
0xEC R/W
PWM Interrupt Flag Register 1
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
BRKLSTS5
BRKLSTS4
BRKLSTS3
BRKLSTS2
BRKLSTS1
BRKLSTS0
23
22
21
20
19
18
17
16
Reserved
BRKESTS5
BRKESTS4
BRKESTS3
BRKESTS2
BRKESTS1
BRKESTS0
15
14
13
12
11
10
9
8
Reserved
BRKLIF5
BRKLIF4
BRKLIF3
BRKLIF2
BRKLIF1
BRKLIF0
7
6
5
4
3
2
1
0
Reserved
BRKEIF5
BRKEIF4
BRKEIF3
BRKEIF2
BRKEIF1
BRKEIF0
Bits
Description
[31:30]
Reserved
Reserved.
[n+24]
n=0,1..5
BRKLSTSn
PWM Channel N Level-detect Brake Status (Read Only)
0 = PWM channel n level-detect brake state is released.
1 = When PWM channel n level-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel n at brake state.
Note:
This bit is read only and auto cleared by hardware. When enabled brake source
return to high level, PWM will release brake state until current PWM period finished. The
PWM waveform will start output from next full PWM period.
[23:22]
Reserved
Reserved.
[n+16]
n=0,1..5
BRKESTSn
PWM Channel N Edge-detect Brake Status
0 = PWM channel n edge-detect brake state is released.
1 = When PWM channel n edge-detect brake detects a falling edge of any enabled brake
source; this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear.
[15:14]
Reserved
Reserved.
[n+8]
BRKLIFn
PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)
0 = PWM channel n level-detect brake event do not happened.
1 = When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1
to clear.
Note:
This bit is write protected. Refer to SYS_REGLCTL register.
[7:6]
Reserved
Reserved.
[n]
n=0,1..5
BRKEIFn
PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)
0 = PWM channel n edge-detect brake event do not happened.
1 = When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1
to clear.
Note:
This bit is write protected. Refer to SYS_REGLCTL register.