Motorola CMOS Logic, Руководство пользователя, Страница: 400 / 571

MOTOROLA CMOS LOGIC DATA MC14536B
6–362
NOTE: When power is first applied to the device, Decode Out can be either at a high or low state.
On the rising edge of a Set pulse the output goes high if initially at a low state. The output
remains high if initially at a high state. Because Clock Inh is held high, the clock source on
the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low
on the first negative clock transition. The output returns high depending on the 8–Bypass,
A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the
number of stages selected from the truth table) is obtainable at Decode Out. A 20–divided
output of IN1 can be obtained at OUT1 and OUT2.
Figure 9. Time Interval Configuration Using an External Clock, Set,
and Clock Inhibit Functions
(Divide–by–2 Configured)
PULSE
GEN.
PULSE
GEN.
CLOCK
8–BYPASS
A
B
C
D
RESET
OSC INH
MONO–IN
SET
CLOCK INH
IN1
VSS
DECODE OUT
OUT 2
OUT 1
8
16
+V
6
9
10
11
12
2
14
15
1
7
3 13
5
4
DECODE OUT
CLOCK INH
SET
IN1
POWER UP
VDD