Motorola CMOS Logic, Руководство пользователя, Страница: 212 / 571

MOTOROLA CMOS LOGIC DATA MC14099B MC14599B
6–174
8-Bit Addressable Latches
The MC14099B and MC14599B are 8–bit addressable latches. Data is
entered in serial form when the appropriate latch is addressed (via address
pins A0, A1, A2) and write disable is in the low state. Chip enable must be
high for writing into MC14599B. For the MC14599B the data pin is a
bidirectional data port and for the MC14099B the input is a unidirectional
write only port. The Write/Read line controls this port in the MC14599B.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip Enable.
A Master Reset capability is available on both parts.
•
Serial Data Input
•
Parallel Output
•
Master Reset
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
•
MC14099B pin for pin compatible with CD4099B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
ÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Parameter
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Value
ÎÎÎ
ÎÎÎ
Unit
ÎÎÎÎ
VDD
ÎÎÎÎÎÎÎÎÎÎÎ
DC Supply Voltage
ÎÎÎÎÎÎ
– 0.5 to + 18.0
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
Vin, Vout
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Input or Output Voltage (DC or Transient)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
– 0.5 to VDD + 0.5
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
Î
ÎÎ Î
ÎÎÎÎ
Iin, Iout
ÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎ Î
ÎÎÎÎÎÎÎÎÎÎÎ
Input or Output Current (DC or Transient),
per Pin
ÎÎÎÎÎÎ
Î
ÎÎÎÎ Î
ÎÎÎÎÎÎ
±
10
ÎÎÎ
Î
Î Î
ÎÎÎ
mA
ÎÎÎÎ
ÎÎÎÎ
PD
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Power Dissipation, per Package†
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
500
ÎÎÎ
ÎÎÎ
mW
ÎÎÎÎ
ÎÎÎÎ
Tstg
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Storage Temperature
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
– 65 to + 150
ÎÎÎ
ÎÎÎ
_
C
ÎÎÎÎ
ÎÎÎÎ
TL
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Lead Temperature (8–Second Soldering)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
260
ÎÎÎ
ÎÎÎ
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
MC14099B MC14599B
13
14
15
16
9
10
11
12 5
4
3
2
1
8
7
6
Q3
Q4
Q5
Q6
VDD
Q0
Q1
Q2
WRITE
DISABLE
DATA
RESET
Q7
VSS
A2
A1
A0
A0
DATA
RESET
Q7
VSS
CE
A2
A1
WRITE
DISABLE
Q4
Q5
Q6
VDD
WRITE/
READ
Q0
Q1
Q2
Q3 14
15
16
17
18
10
11
12
13
5
4
3
2
1
9
8
7
6
PIN ASSIGNMENT
PIN ASSIGNMENT
CHIP ENABLE
WRITE/READ
WRITE DISABLE
DATA
A0
A1
A2
RESET
8
10
4
3
2
5
6
7
DECODER
11
12
13
14
15
16
17
1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
8
LATCHES
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
8
LATCHES
DECODER
5
6
7
WRITE DISABLE
DATA
A0
A1
A2
RESET
8
4
3
2
8
VDD = 18
VSS = 9
VDD = 16
VSS = 8
9
10
11
12
13
14
15
1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14099B
MC14599B
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14099BCP Plastic
MC14099BCL Ceramic
MC14099BDW SOIC
TA = – 55
°
to 125
°
C for all packages.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
L SUFFIX
CERAMIC
CASE 726
ORDERING INFORMATION
MC14599BCP Plastic
MC14599BCL Ceramic
P SUFFIX
PLASTIC
CASE 707
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
v
(Vin or Vout)
v
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
TA = – 55
°
to 125
°
C for all packages.