SmartTime Static Timing Analyzer User Guide
90
false_path.v
/////////////////////////////////////////////////////////
// Company: Microsemi Corp
//
// File history:
// 0.1 Initial Version
//
// Description:
// Simple example design to demonstrate use of timing
//
constraints.
//
// Targeted device: Family::SmartFusion2; Die::M2S050;
//
Package::484 FBGA;
//
// Author: Vishakh Rayapeta
//
////////////////////////////////////////////////////////////
module false_path (D0, D1, D2, RST, CLK, Q);
input D0;
input D1;
input D2;
input RST;
input CLK;
output Q;
reg D0_reg;
reg D0_inv_reg;
reg D1_reg;
reg D2_reg;
reg Q_reg;
wire XOR2 /*synthesis syn_keep=1*/;
wire AND2 /*synthesis syn_keep=1*/;
wire OR2 /*synthesis syn_keep=1*/;
wire MUX2 /*synthesis syn_keep=1*/;
wire NOT1 /*synthesis syn_keep=1*/;
wire NOT2 /*synthesis syn_keep=1*/;
assign Q = Q_reg /*synthesis syn_keep=1*/;
always @(posedge CLK or posedge RST)
begin
if (RST)
begin
D0_reg <= 1'b0;
D0_inv_reg <= 1'b0;
end
else
begin
D0_reg <= D0;
D0_inv_reg <= ~D0;
end
end
assign XOR2 = D0_reg ^ D0_inv_reg;
assign OR2 = D0_inv_reg || D1_reg;
assign AND2 = OR2 && D2_reg;
assign MUX2 = (XOR2) ? (D2_reg) : (AND2);
always @(posedge CLK)
begin
D1_reg <= D1;
D2_reg <= D2;
Содержание SmartTime
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Страница 37: ...SmartTime Static Timing Analyzer User Guide 37 Generating Timing Reports ...
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Страница 92: ...SmartTime Static Timing Analyzer User Guide 92 Dialog Boxes ...
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