SmartTime Static Timing Analyzer User Guide
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Figure 33 · Cross-Probing – Timing Path
Alternatively, right-click a path in the Max/Min Delay Analysis View and select
Show Path in Chip Planner
to cross-probe the path.
Figure 34 · Cross-Probing Path from Max/Min Delay Analysis View Table
Port Example
1. Make sure that the design has successfully completed the Place and Route step.
2. Open the SmartTime Maximum/Minimum Analysis View.
3. Open Chip Planner.
4. In the SmartTime Maximum/Minimum Analysis View, right-click the Port “CLK” in the Path and choose
Show in Chip Planner
. Note that the Port “CLK” is selected and highlighted in the Chip Planner Port
View.
Note
: Show in Chip Planner is grayed out if Chip Planner is not already open.
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