SmartTime Static Timing Analyzer User Guide
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Timing Exceptions Overview
Use timing exceptions to overwrite the default behavior of the design path. Timing exceptions include:
•
Setting multicycle constraint to specify paths that (by design) will take more than one cycle.
•
Setting a false path constraint to identify paths that must not be included in the timing analysis or the
optimization flow.
•
Setting a maximum delay constraint on specific paths to relax or to tighten the original clock constraint
requirement.
Clock Skew
The clock skew between two different sequential components is the difference between the insertion delays
from the clock source to the clock pins of these components. SmartTime calculates the arrival time at the
clock pin of each sequential component. Then it subtracts the arrival time at the receiving component from
the arrival time at the launching component to obtain an accurate clock skew.
Both setup and hold checks must account for clock skew. However, for setup check, SmartTime looks for
the smallest skew. This skew is computed by using the maximum insertion delay to the launching sequential
component and the shortest insertion delay to the receiving component.
For hold check, SmartTime looks for the largest skew. This skew is computed by using the shortest insertion
delay to the launching sequential component and the largest insertion delay to the receiving component.
SmartTime makes this distinction automatically.
Cross Probing
Design objects displayed in SmartTime can be cross-probed into other Libero SoC tools. Libero SoC allows
cross-probing from SmartTime to the Constraints Editor (but not vice versa) and from SmartTime to Chip
Planner (but not vice versa). When cross-probing from SmartTime to one of the other tools, both SmartTime
and the other tool must first be opened.
From SmartTime to Constraint Editor
You can add a timing exception constraint from SmartTime and have the Constraints Editor display the
Constraint. From the SmartTime Maximum or Minimum Delay Analysis View, click a timing path to add a
timing exception constraint. When the Constraints Editor’s Add Constraint dialog box opens, the fields for
source (from) pin and destination (to) pin are populated with the correct names from the timing path you
have selected.
To add a timing exception constraint from a timing path in SmartTime Max/Min Delay Analysis View:
1. Open SmartTime (
Design Flow Window > Verify Timing > Open interactively
).
2. Open the Constraints Editor (
Constraint Manager > Timing Tab > Edit with Constraints Editor
).
3. Select Max/Min Delay Analysis View and right-click a timing path in the table.
4. Select a timing exception constraint to add: False Path Constraint, Maximum Delay Constraint,
Minimum Delay Constraint, or Multicycle Path Constraint.
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