SmartTime Static Timing Analyzer User Guide
108
Sets Pane
Figure 87 · Timing Bottleneck Report - Sets Pane Dialog Box
This pane has four mutually exclusive options:
•
Entire Design
•
Clock Domain
•
Use existing user set
•
Use Input to Output Set
Entire Design
: Select this option to display the bottleneck information for the entire design.
Clock Domain
: Select this option to display the bottleneck information for the selected clock domain. You
can specify the following options:
•
Clock: Allows pruning based on a given clock domains. Only cells that lie on these violating paths are
reported.
•
Type: This option can only be used in conjunction with -clock. The acceptable values are:
Value
Description
Register to Register
Paths between registers in the design
Asynchronous to Register
Paths from asynchronous pins to registers
Register to Asynchronous
Paths from registers to asynchronous pins
External Recovery
The set of paths from inputs to asynchronous pins
External Setup
Paths from input ports to register
Clock to Output
Paths from registers to output ports
Use existing user set
: Displays the bottleneck information for the existing user set selected. Only paths that
lie within the name set are will be considered towards the bottleneck report.
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