SmartTime Static Timing Analyzer User Guide
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Cross-Probing Examples
To cross-probe from SmartTime to Chip Planner, a design macro in SmartTime is used.
Design Macro Example
1. Make sure that the design has successfully completed the Place and Route step.
2. Open SmartTime Maximum/Minimum Analysis View.
3. Open Chip Planner.
4. In the SmartTime Maximum Analysis View, right-click the instance Q[2] in the Timing Path Graph and
choose
Show in Chip Planner
. Note that with cross-probing, the Q[2] macro is selected in Chip
Planner’s Logical View and highlighted (white) in the Chip Canvas. The Properties window in Chip
Planner displays the properties of Q[2].
Note
: Show in Chip Planner is grayed out if Chip Planner is not already open.
Note
: You may need to zoom in to view the highlighted Q2 Macro in the Chip Canvas.
Figure 32 · Cross-Probing – Macro
Timing Path Example
1. Make sure that the design has successfully completed the Place and Route step.
2. Open the SmartTime Maximum/Minimum Analysis View.
3. Open Chip Planner.
4. In the SmartTime Maximum/Minimum Analysis View, right-click the net CLK_ibuf/U0/U_IOPAD:PAD in
the Table and choose
Show Path in Chip Planner
. Note that the net is selected (highlighted in red) in
the Chip Canvas view and the three macros connected to the net are also highlighted (white) in the
Chip Canvas view.
Note
: Show Path in Chip Planner is grayed out if Chip Planner is not already open.
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