SmartTime Static Timing Analyzer User Guide
82
•
Speed
: STD
•
Die Voltage
: 1.2 V
•
Range
: COM
3. Click
Finish
to create the new project.
4. At the pop-up window, click
Use Enhanced Constraint Flow
in the New Project Information dialog
box.
Figure 60 · New Project Information Dialog Box
Import the false_path Verilog File and Add Constraints
You must import the false_path.v Verilog source file into your design for this tutorial. Cut-and-paste the
Verilog program from
false_path.v
to a file of the same name in a local directory.
Then run Libero SoC.
To import the Verilog Source File:
1. From the
File
menu, choose
Import > HDL Source Files
.
2. Browse to the location of the false_path.v you saved and select it. Click
Open
to import the file.
3. Verify that the file appears in your project, as shown in the figure below.
Содержание SmartTime
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