Intel 855PM, Руководство по конструкции, Страница: 45 / 372

FSB Design Guidelines
R
Intel
®
855PM Chipset Platform Design Guide
45
Table 6. FSB Address Source Synchronous Signal Trace Length Mismatch Mapping
CPU Signal Name Signal Matching Strobe Associated With the Group
Strobe to Assoc. Address
Signal Matching
Notes
REQ[4:0]#, A[16:3]# ± 200 mils ADSTB0# ± 200 mils 1, 2
A[31:17]# ± 200 mils ADSTB1# ± 200 mils 1, 2
NOTES:
1.
ADSTB[1:0]# should be trace length matched to the average length of their associated Address signals group.
2.
Each Address signal should be trace length matched to its associated Address Strobe within ± 200 mils.
Table 7 lists the source synchronous address signals general routing requirements. Due to the 200-MHz,
high frequency operation of the address signals, 1:3 spacing is strongly advised and trace lengths should
be limited to a pin-to-pin trace length minimum of 0.5 inches and a maximum of 6.5 inches. The routing
guidelines listed in Table 7 allows for 1:2 spacing for the address signals given a 55
± 15%
characteristic trace impedance. But if space permits, 1:3 spacing should be applied to these signals. For
the address strobes, 1:3 spacing is required irrespective of the tolerance of the trace impedance. This is a
change from previous recommendations where 1:2 spacing was acceptable for ± 15% impedance
tolerances.
Table 7. FSB Source Synchronous Address Signal Routing Guidelines
Signal Names Total Trace Length
CPU MCH
Transmission
Line Type
Min
(inches)
Max
(inches)
Nominal
Impedance
( )
Width & Spacing
(mils)
A[31:3]# HA[31:3]# Strip-line 0.5 6.5 55 ± 15% 4 & 8
REQ[4:0]# HREQ[4:0]# Strip-line 0.5 6.5 55 ± 15% 4 & 8
ADSTB#[1:0] HADSTB[1:0]# Strip-line 0.5 6.5 55 ± 15% 4 & 12
4.1.3.4. Source Synchronous Signals Recommended Layout Example
Figure 11 illustrates escape routing of the FSB source synchronous signals in the vicinity of the Intel
855PM MCH package. The primary side has minimum length dog bones from the BGA lands that
transition with vias into internal routing Layer 3 and Layer 6. Note the change in orientation of the dog
bone “dipoles” as it changes from place to place to allow smooth escape routing on Layer 3 and Layer 6
later on in between the GND vias. The signals are split about half and half between Layer 3 and Layer 6.
For address signals, the first group containing REQ[4:0]#, A[16:3]#, and ADSTB[0]# are routed on
Layer 3. The second group of address signals containing A[31:17]# and ADSTB[1]# is routed on Layer
6. Similarly, D[15:0]#, DINV[0]#, DSTBN[0]#, DSTBP[0]# and D[47:32]#, DINV[2]#, DSTBN[2]#,
DSTBP[2]# are routed on Layer 3. The remaining two data signals groups with associated strobe and
DINV signals are routed on Layer 6. A vertical corridor with no routing on Layer 6 to the left of the
D[63:48]# group is used to feed the 1.2-V core power plane of the MCH.
Figure 11 also illustrates how a horizontal corridor with no routing on Layer 3 in between the address
and data signals allows feeding of the VCCA (1.8 V) power plane to the PLL power delivery pins
VCCGA and VCCHA of the Intel 855PM MCH and continues to the VCCA[3:0] pins of the processor.
Notice that this 1.8-V VCCA power plane “forks” as a separate branch from the 1.8-V decoupling
capacitor while the Hub Interface (HI) 1.8-V power pins connect to a separate branch of the 1.8-V
power plane flood on Layer 3. This is done to reduce noise pickup of the PLL power delivery due to HI
switching activity.