Intel 855PM, Руководство по конструкции

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Platform Power Delivery Guidelines
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Intel
®
855PM Chipset Platform Design Guide
11.5.4. DDR SMRCOMP Resistive Compensation
The Intel 855PM MCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer
characteristics to specific board and operation environment characteristics. Refer to the
Intel
®
855PM
Memory Controller Hub (MCH) DDR 200/266 MHz Datasheet
for details on resistive compensation.
Tie the SMRCOMP pin of the MCH to a 30.1- ± 1% pull-up resistor to the DDR termination voltage
(1.25 V). Also, one 0603 0.1-µF decoupling capacitor to ground should be used. Place the resistor and
capacitor within 1.0 inch of the MCH. The decoupling capacitor
must
be placed on the VTT powered
side of the SMRCOMP resistor. The SMRCOMP signal and VTT trace should be routed with as wide a
trace as possible. It should be a minimum of 12 mils wide and be isolated from other signals with a
minimum of 10 mils spacing.
11.5.5. DDR VTT Termination
The recommended topology for DDR-SDRAM Data, Control, and Command signal groups requires that
all these signals to be terminated to a 1.25-V source, VTT, at the end of the memory channel opposite
the Intel 855PM MCH. It is recommended that VTT be generated from the same source as that used for
VCCSM, and do not be shared with the MCH and DDR SMVREF. SMVREF has a much tighter
tolerance and VTT can vary more easily depending on signal states. A solid 1.25-V termination island
should be used to for this purpose. The VTT termination island should be placed on the top signal layer,
just beyond the last SO-DIMM connector and must be at least 50 mils wide. The Data and Command
signals should be terminated using one resistor per signal. Resistor packs and ± 5% tolerant resistors are
acceptable for this application. Only signals from the same DDR signal group can share a resistor pack.
See Section 11.5.1 and 11.7.1 for details on high frequency and bulk decoupling requirements.
11.5.6. DDR SMRCOMP, SMVREF, VTT 1.25-V Supply Disable in
S3/Suspend
The DDR interface of the Intel 855PM MCH requires that several 1.25-V voltage sources be supplied to
different parts the system memory interface for proper operation. In addition to providing the DDR VTT
termination voltage at the end of the DDR bus for the Data, Control, and Command signal groups, 1.25-
V supplies are also used to provide the reference voltages SMVREF of the MCH, the VREF of the DDR
memory devices on the SO-DIMMs, and the termination voltage of the 30.1
± 1% SMRCOMP
resistor of the MCH.
SMRCOMP and VTT 1.25-V supplies can be disabled during the S3 suspend state to further save power
on the platform. This is possible because the MCH does not require resistive compensation during
suspend. However, the 2.5-V VCCSM power pins of the MCH, the
SMVREF
pin of the MCH, and the
VDD power pins of the DDR memory devices are required to be on in S3 state.
Note:
Some DDR memory devices require a valid reference voltage during suspend. It is the responsibility of
the system designer to ensure that requirements of the DDR memory devices are met. Intel recommends
following VREF design on Intel CRB.
11.5.6.1. VTT Rail Power Down Sequencing During Suspend
The VTT termination voltage for the DDR bus must not be turned off until all populated rows of
memory have been placed into power down mode through the deassertion of the SCKE signals. Once all