Intel 855PM, Руководство по конструкции

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FSB Design Guidelines
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Intel
®
855PM Chipset Platform Design Guide
41
4.1.3. Source Synchronous Signals
All source synchronous signals use an AGTL+ bus driver technology with on-die GTL termination
resistors connected in a point-to-point, Zo = 55
controlled impedance topology between the Intel
Pentium M/Intel Celeron M processor and the Intel 855PM MCH. No external termination is needed on
these signals. Source synchronous FSB address signals operate at a double pumped rate of 200 MHz
while the source synchronous FSB data signals operate at a quad pumped rate of 400 MHz. High-speed
operation of the source synchronous signals requires careful attention to their routing considerations.
The following guidelines should be strictly adhered to, to guarantee robust high-frequency operation of
these signals.
4.1.3.1. Source Synchronous General Routing Guidelines
Source synchronous data and address signals and their associated strobes are partitioned into groups of
signals. Flight time skew minimization within the same group of source synchronous signals is a key
parameter that allows their high frequency (400 MHz) operation. All the source synchronous signals that
belong to
the same group
should be routed on
the same internal layer
for the entire length of the bus.
It is acceptable to split different groups of source synchronous signals between different motherboard
layers as long as all the signals that belong to that group are kept on the same layer. Grouping of FSB
source synchronous signals is summarized in Table 3 and Table 6. This practice results in a significant
reduction of the flight time skew since the dielectric thickness, line width, and velocity of the signals
will be uniform across a single layer of the stack-up. There is no guarantee of a relationship of dielectric
thickness, line width, and velocity between layers.
The source synchronous signals should be routed as a strip-line on an internal layer with complete
reference to ground planes both above and below the signal layer. Routing with references to split
planes or power planes other than ground is not allowed. For the recommended stack-up example as
shown in Figure 2, source synchronous FSB signals are routed on Layer 3 and Layer 6. Layer 2 and
Layer 7 are solid grounds across the entire motherboard. However, this is not sufficient since significant
coupling exists between signal Layer 3 and power plane Layer 2 as well as signal Layer 6 and power
plane Layer 5. To guarantee complete ground referencing, Layer 4 and Layer 5 are converted to ground
plane floods in the areas where the source synchronous FSB signals are routed. In addition all the
ground plane areas are stitched with ground vias in the vicinity of the processor and Intel 855PM MCH
package outlines with the vias of the ground pins of the processor and MCH pin-map.
Figure 9 illustrates a motherboard layout and a cross-sectional view of the recommended stack-up of the
FSB source synchronous DATA and ADDRESS signals referencing ground planes on both Layer 7 and
Layer 5. Notice that in the socket cavity of the processor Layer 5 and Layer 6 layers is used for VCC
core power delivery. However, outside the socket cavity Layer 6 signals are routed on top of a solid
Layer 7 ground plane and also Layer 5 is converted to a ground flood under the shadow of the FSB
signals routing between the processor and MCH. Stitching of all the GND planes is provided by the
ground vias in the pin-map of the processor and MCH.