Intel 855PM, Руководство по конструкции

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System Memory Design Guidelines (DDR-SDRAM)
R
Intel
®
855PM Chipset Platform Design Guide
125
6. System Memory Design Guidelines
(DDR-SDRAM)
The Intel 855PM chipset Double Data Rate (DDR) SDRAM system memory interface consists of 121
CMOS signals. These CMOS signals have been divided into several signal groups: Data, Command,
Control, Feedback, and Clock signals. Table 23 summarizes the different signal grouping. Refer to the
Intel
®
855PM Memory Controller Hub (MCH) DDR 200/266/MHz Datasheet
for details on the signals
listed.
Table 23. Intel 855PM Chipset DDR Signal Groups
Group Signal Name Description
SDQ[63:0] Data Bus
SDQ[71:64] Check Bits for ECC Function
Data
SDQS[8:0] Data Strobes
SMA[12:0] Memory Address Bus
SBS[1:0] Bank Select
SRAS# Row Address Select
SCAS# Column Address Select
Command
SWE# Write Enable
SCKE[3:0] Clock Enable - (One per Device Row)
Control
SCS#[3:0] Chip Select - (One per Device Row)
RCVENOUT# Output Feedback Signal
Feedback
RCVENIN# Input Feedback Signal
SCK[5:0] DDR-SDRAM Differential Clocks - (3 per SO-DIMM)
Clocks
SCK#[5:0] DDR-SDRAM Inverted Differential Clocks - (3 per SO-DIMM)