Intel 855PM, Руководство по конструкции

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Platform Power Requirements
R
Intel
®
855PM Chipset Platform Design Guide
119
The left side of Figure 67 illustrates how the conceptual cross section (right side of Figure 67) of the
V
CCP
(1.05 V) plane for power delivery for the Intel 855PM MCH translates into an actual layout. The
entire section of the MCH pin-map related to the FSB signals is a flood with a V
CCP
plane on the
secondary side (Layer 8). Five 0603 form factor 0.1-µF capacitors are placed next to each of the V
CCP
pins of the MCH pin-map on the inner rows. The V
CCP
pad of the capacitor is placed within (center-to-
center) 45 mils of the inner row of V
CCP
pins on the MCH pin-map. All the capacitors in the MCH’s
inner row of power pins are to be spaced 70 mils from each other to allow adequate spacing and
placement of the capacitors. The groundsides of the 0.1-µF capacitors are shorted with a “ring” shaped
ground flood. The groundside vias are within 45 mils of each of the ground pads of the capacitors. See
the “Zoom In View” in Figure 67. Three, 0.1-µF 0603 form factor capacitors are placed outside the
MCH cavity on the secondary side. It is important that the layout style and placement of the 0603 form
factor capacitors for V
CCP
as explained above in Figure 67 are closely followed to guarantee the 0.6 nH
ESL for these capacitors. For clarity, refer to the “Zoom In View” picture of the capacitor placement on
the MCH’s secondary side on the inner row pin field as illustrated on the right side of Figure 68.
One, 150-µF POSCAP placed on the secondary side (top right corner of Figure 67) close to the MCH
package body outline should also be used.
Figure 68. Intel 855PM MCH V
CCP
Power Delivery Recommended Layout (Zoom In View)
VCCP=1.05v
Secondary Side
GND
VCCP=1.05v
1.2v
2.5v
1.8v
1.5v
5.9.5. Intel 855PM MCH Core Voltage Plane and Decoupling
The V
CC-MCH
(1.2 V) plane feeds the internal core logic of the 855PM MCH. V
CC-MCH
does not employ
on package decoupling. Thus, in order to guarantee an accurate V
CC-MCH
voltage on the MCH die, the
specific decoupling guidelines listed in Table 22 should be closely adhered to. The specific component
form factors, the layout style, and the decoupling capacitor values should also be used with no deviation
from recommendations.
The decoupling for V
CC-MCH
should utilize two, 150-µF POSCAPs acting as bulk decoupling capacitors
and should be placed (preferably) on the secondary side of the motherboard in the vicinity of the MCH
package shadow. The mid frequency decoupling should include a 2.2-µF, 10% 0805 form factor X7R
MLCC decoupling capacitor placed within 50 mils of the MCH’s U16 V
CC-MCH
pin. High frequency
decoupling consists of the careful tuning of five 0603 form factor X7R capacitors with different values
each: One, 0.22-µF, 10% capacitor; one, 47-nF, 10% capacitor; one, 22-nF, 10% capacitor; one, 15 nF,