Intel 855PM, Руководство по конструкции, Страница: 238 / 372

Platform Clock Routing Guidelines
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238
Intel
®
855PM Chipset Platform Design Guide
Table 65. AGPCLK Routing Guidelines
Parameter Routing Guidelines Figure Notes
Signal Group AGPCLK 1
Motherboard Topology Point-to-Point
Reference Plane
Ground Referenced (Contiguous over entire
length)
Characteristic Trace Impedance (Zo) 55 ± 15%
Trace Width 4 mils
Trace to Space Ratio 1:5 (e.g. 4 mils trace 20 mils space)
Group Spacing
Isolation spacing from non-Clock signals =
20 mils minimum
Trace Length – A Trace length matched to CLK66 Trace A
Figure 132,
Figure 133
2
Trace Length – B (Option #1)
Must be exactly trace length matched to
CLK66 Trace B
Figure 133 3
Trace Length – B (Option #2)
Must be exactly trace length matched to
[(CLK66 Trace B) - 4.0 inches]
Figure 132 4
Trace Length – C Routed 4.0 inches per the AGP Specification Figure 132
Series Termination Resistor (R1) 33 ± 5% Figure 133
Skew Requirements
Minimal skew (~ 0) between AGPCLK and
CLK66 group
NOTES:
1.
Recommended resistor values and trace lengths may change in a later revision of the design guide.
2.
AGPCLK Trace A should be trace length matched to CLK66 Trace A as closely as possible.
3.
To achieve minimal skew for AGP device down topologies, AGPCLK Trace B should be matched as closely to
CLK66 Trace B as possible.
4.
To achieve minimal skew for AGP connector topologies, AGPCLK Trace B should be matched as closely to
CLK66 Trace B as possible. Note that Trace C is assumed to be 4.0 inches on the AGP card and should be
subtracted from the AGPCLK Trace B length when matching to CLK66 Trace B.
10.2.4. CLK33 Clock Group
The driver is the clock synthesizer 33-MHz clock output buffer and the receiver is the 33-MHz clock
input buffer at the ICH4-M, FWH, and SIO.
Note:
The goal is to have minimal (~ 0) skew between the clocks within this group, and also minimal (~ 0)
skew between the clocks of this group and that of group CLK66.