Intel 855PM, Руководство по конструкции

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FSB Design Guidelines
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Intel
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855PM Chipset Platform Design Guide
4.1.2. Common Clock Signals
All common clock signals use an AGTL+ bus driver technology with on die integrated GTL termination
resistors connected in a point-to-point, Zo = 55
, controlled impedance topology between the processor
and the Intel 855PM chipset MCH. No external termination is needed on these signals. These signals
operate at the FSB frequency of 100 MHz.
Common clock signals should be routed on an internal or external layer while referencing solid ground
planes. Common clock signal routing on internal layers implemented with complete reference to ground
planes both above and below the signal layer is recommended. Based on current simulation results,
routing on internal layers allows for a minimum pin-to-pin motherboard length of 1.0 inch and a
maximum of 6.5 inches. Routing on external layers allows for a pin-to-pin motherboard length of 1.0
inch and a maximum of 6.5 inches. Trace length matching for the common clock signals is not required.
Intel recommends routing these signals on the same internal or external layer for the entire length of the
bus. If routing constraints require routing of these signals with a transition to a different layer, a
minimum of one ground stitching via for every two signals should be placed within 100 mils of the
signal transition vias.
Routing of the common clock signals should use a minimum of 1:2 trace spacing. This implies a 4-mil
trace width with a minimum of 8-mil spacing (i.e. 12-mil minimum pitch) for routing on internal layers.
For external layers, route using a 5-mil trace width and a 10-mil minimum spacing (i.e. 15-mil pitch).
Practical cases of escape routing under the MCH or the processor package outline and near by vicinity
may not allow the implementation of 1:2 trace spacing requirements. Although every attempt should be
made to maximize the signal spacing in these areas, it is allowable to have 1:1 trace spacing underneath
the MCH and the processor package outlines and up to 200 – 300 mils outside the package outline.
Table 1 summarizes the list of common clock and key routing requirements. RESET# (CPURST# of
MCH) is also a common clock signal but requires a special treatment for the case where an
ITP700FLEX debug port is used. See Section 4.1.5 for further details. Figure 6 and Figure 7 illustrate
an example of escape routing from the processor and the Intel 855PM chipset MCH package vicinity for
the common clock signals. To allow for flat routing, DEFER#, DRDY#, HIT#, HITM#, TRDY#, and
BNR# would have to have minimal routing on the primary side in the vicinity of the MCH package and
then the rest of the routing continues on internal layer 6. The ground vias of the MCH pins provide the
needed ground stitching vias for a layer transition for these signals. The remaining signals have standard
dog bone (a land for a BGA ball followed by a short trace to a via with a 25-mil offset in the X and Y
directions) vias on the primary side and continue to the processor in a simple point-to-point connection.
The processor only has straightforward dog bones on the primary side for this group of signals. Figure 8
shows a global routing summary of these common clock signals as a simple point-to-point connection
on Layer 6 between the processor and the Intel 855PM MCH.