Intel 855PM, Руководство по конструкции

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Platform Clock Routing Guidelines
R
234
Intel
®
855PM Chipset Platform Design Guide
1.
Recommended resistor values and trace lengths may change in a later revision of the design guide.
2.
This number does not include clock driver common mode.
3.
The skew budget includes clock driver output pair to output pair jitter (differential jitter), and skew, clock skew
due to interconnect process variation, and static skew due to layout differences between clocks to all bus agents.
4.
The interconnect portion of the total budget for this specification assumes clock pairs are routed on multiple
routing layers and routed no longer than the maximum recommended lengths.
5.
Skew measured at the load between any two, bus agents. Measured at the crossing point.
6.
Edge-to-edge spacing between the two traces of any differential pair. Uniform spacing should be maintained
along the entire length of the trace.
7.
Clock traces are routed in a differential configuration. Maintain the minimum recommended spacing between the
two traces of the pair. Do not exceed the maximum trace spacing, as this will degrade the noise rejection of the
network.
8.
Set the line width to meet correct system board impedance. The line width value provided here is a
recommendation to meet the proper trace impedance based on the recommended stack-up.
9.
The differential impedance of each clock pair is approximately 2*Z single-ended*(1-2*Kb) where Kb is the
backwards crosstalk coefficient. For the recommended trace spacing, Kb is very small and the effective
differential impedance is approximately equal to 2 times the single-ended impedance of each half of the pair.
10.
The single ended impedance of both halves of a differential pair should be targeted to be of equal value. They
should have the same physical construction. If the BCLK traces vary within the tolerances specified, both traces
of a differential pair must vary equally.
11.
Values are based on socket dimensions/tolerances/parasitics outlined in the
Intel® Mobile Processor Micro-
FCPGA Socket (mPGA479M) Design Guidelines (Order number: 298520)
. Or in general terms, a 4mm ± 5%
socket with lumped parasitics model. Length compensation for the processor socket and package delay is added
to chipset routing to match electrical lengths between the chipset and the processor from the die pad of each.
Therefore, the system board trace length for the chipset will be longer than that for the processor. e.g. If Clock
Driver-to-MCH = 4.0” then Clock Driver-to-Processor = 3.6” ± 50 mils.
12.
Rs value of 33 Ω has shown to be an effective solution.
13.
Rt shunt termination value should match the system board impedance.
14.
Minimize L1, L2 and L3 lengths. Long lengths on L2 and L3 degrade effectiveness of source termination and
contribute to ring back.
15.
The goal of constraining all bus clocks to one physical routing layer is to minimize the impact on skew due to
variations in Er and the impedance variations due to physical tolerances of circuit board material.
16.
Minimize the trace length difference between L1/L1’ of the processor and MCH BCLK/BCLK# pair to minimize
skew. Length matching of L1/L1’ within 10 mils should be between the shortest BCLK/BCLK# signal of one pair
to the longest BCLK/BCLK# signal of the other pair.
10.2.1.1. BCLK Length Matching Requirements
To compensate for the extra delay introduced by the processor socket dimensions/tolerances/parasitics
as well as the package parasitics, the Clock Driver-to-MCH (L1 + L2 + L4) motherboard routing will be
longer than Clock Driver-to-Processor (L1 + L2 + L4) motherboard routing.
Clock Driver-to-MCH
routing should be 400 mils ± 50 mils longer than Clock Driver-to-Processor routing
. i.e. the
following relationship should be adhered to:
Clock Driver-to-Processor (L1 + L2 + L4) = Clock Driver-to-MCH (L1 + L2 + L4) – 400 mils ± 50 mils
In order to minimize the clock skew between the processor and the MCH, the L1/L1’ segments of the
two FSB agents should be exactly trace length matched if possible. The routing should be done such that
the shortest L1/L1’ segment of the processor is matched within ± 10 mils of the longest L1/L1’ segment
of the MCH. i.e. the following relationship should be adhered to:
Processor shortest(L1/L1’) = MCH longest(L1/L1’) ± 10 mils.
Additionally, the routing of each half of the host clock pair for the processor and MCH should be trace
length matched within ± 10 mils of its complement’s routing. i.e. the following relationships should be
adhered to:
Processor (L1 + L2 + L4) = Processor (L1’ + L2’ + L4’) ± 10 mils
and