Automationdirect.com DL05, Руководство пользователя

Страница: 135 / 480

High-Speed Input and
Pulse Output Features
3–49
High-Speed Input and Pulse Output Features
Mode 50: Pulse Catch Input
The HSIO circuit has a pulse-catch mode of operation. It monitors the signal on input
X0, preserving the occurrence of a narrow pulse. The purpose of the pulse catch
mode is to enable the ladder program to “see” an input pulse which is shorter in
duration than the current scan time. The HSIO circuit latches the input event on input
X0 for one scan. This contact automatically goes off after one scan.
Refer to the block diagram below. When the lower byte of HSIO Mode register V7633
contains a BCD “50”, the pulse catch mode in the HSIO circuit is enabled. X0
automatically becomes the pulse catch input, which sets the latch on each rising
edge. The HSIO resets the latch at the end of the next CPU scan. Inputs X1 and X2
are available as filtered discrete inputs.
Output Circuit
Input Circuit
CPU
PLC
DL05
X0
Y0, Y1
X3- X7
Y2 - Y5
VĆmemory
V7633 0050
Mode Select
I/O data
HSIO
LATCH
Set Reset
X1, X2
scan
FILTER
Signal pulses at X0 must meet certain timing criteria to guarantee a pulse capture
will result. Refer to the timing diagram below. The input characteristics of X0 are
fixed (it is not a programmable filtered input). The minimum pulse width is 0.1 mS.
There must be some delay before the next pulse arrives, such that the pulse period
cannot be smaller than 0.5 mS. If the pulse period is smaller than 0.5 mS, the next
pulse will be considered part of the current pulse.
Time
Pulse
Input
X0
0.1 mS minimum
0.5 mS minimum
Note that the pulse catch and filtered input functions are opposite in nature. The
pulse catch feature on X0 seeks to
capture narrow pulses, while the filter input
feature on X1 and X2 seeks to reject narrow pulses.
Purpose
Functional Block
Diagram
Pulse Catch
Timing Parameters