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UG-1262
Rev. B | Page 7 of 312
First Master Address Byte Register ....................................... 234
Second Master Address Byte Register ................................... 234
Serial Clock Period Divisor Register ..................................... 235
Slave Control Register ............................................................. 235
C Status, Error, and IRQ Register ............................. 236
Slave Receive Register .............................................................. 237
Slave Transmit Register ........................................................... 237
Hardware General Call ID Register ....................................... 237
First Slave Address Device ID Register ................................. 237
Second Slave Address Device ID Register ............................ 238
Third Slave Address Device ID Register ............................... 238
Fourth Slave Address Device ID Register ............................. 238
Master and Slave FIFO Status Register ................................. 238
Master and Slave Shared Control Register ........................... 239
Serial Peripheral Interfaces ......................................................... 241
SPI Features .............................................................................. 241
SPI Overview ............................................................................ 241
SPI Operation ........................................................................... 241
SPI Transfer Initiation ............................................................ 242
SPI Interrupts ........................................................................... 244
SPI Wire-OR’ed Mode ............................................................ 245
SPI CSERR Condition ............................................................. 245
SPI DMA ................................................................................... 245
SPI and Power-Down Modes ................................................. 246
Register Summary: SPI0/SPI1 .................................................... 247
Register Details: SPI0/SPI1 ......................................................... 248
Status Registers ......................................................................... 248
Receive Registers ...................................................................... 249
Transmit Registers ................................................................... 249
Baud Rate Selection Registers ................................................ 249
Configuration Registers .......................................................... 250
Interrupt Configuration Registers ......................................... 251
Transfer Byte Count Registers ............................................... 252
DMA Enable Registers ............................................................ 252
FIFO Status Registers .............................................................. 253
Read Control Registers ............................................................ 254
Flow Control Registers ............................................................ 255
Wait Timer for Flow Control Registers ................................ 255
Chip Select Override Registers ............................................... 255
UART Serial Interface .................................................................. 256
UART Overview ........................................................................ 256
UART Features .......................................................................... 256
UART Operation ...................................................................... 256
Register Summary: UART ........................................................... 259
Register Details: UART ................................................................ 260
Transmit Holding Register ...................................................... 260
Receive Buffer Register ............................................................ 260
Interrupt Enable Register ........................................................ 260
Interrupt Identification Register ............................................ 261
Line Control Register ............................................................... 261
Modem Control Register ......................................................... 262
Line Status Register .................................................................. 262
Modem Status Register ............................................................ 263
Scratch Buffer Register ............................................................. 263
FIFO Control Register .............................................................. 263
Fractional Baud Rate Register ................................................. 264
Baud Rate Divider Register ..................................................... 264
Second Line Control Register ................................................. 264
UART Control Register ........................................................... 265
Receive FIFO Count Register .................................................. 265
Transmit FIFO Count Register ............................................... 265
RS485 Half-Duplex Control Register ..................................... 265
Autobaud Control Register ..................................................... 266
Autobaud Status (Low) Register ............................................. 266
Autobaud Status (High) Register ........................................... 266
Digital Die General-Purpose Timers ......................................... 267
Digital Die General-Purpose Timers Features ..................... 267
General-Purpose Timers Overview ........................................ 267
General-Purpose Timer Operations ...................................... 267
Register Summary: General-Purpose Timers ........................... 270
Register Details: General-Purpose Timers ................................ 271
16-Bit Synchronous Load Value Registers ............................ 271
16-Bit Timer Synchronous Value Registers .......................... 271
Control Registers ...................................................................... 271
Clear Interrupt Registers ......................................................... 272
Capture Registers ...................................................................... 272
16-Bit Asynchronous Load Value Registers ......................... 273
16-Bit Timer Asynchronous Value Registers ....................... 273
Status Registers .......................................................................... 273
Analog Die General-Purpose Timers ......................................... 274