UM012811-0904
eZ8 CPU Instruction Set Description
eZ8 CPU
User Manual
182
TCM
Test Complement Under Mask
TCM dst, src
Operation
(NOT dst) AND src
Description
This instruction tests selected bits in the destination operand for a logical 1 value. Specify
the bits to be tested by setting a 1 bit in the corresponding bit position in the source oper-
and (the mask). The TCM instruction complements the destination operand and AND’s it
with the source mask (operand). Check the Zero flag to determine the result. If the Z flag
is set, the tested bits were 1. When a TCM operation is completed, the destination and
source operands retain their original values.
Flags
Attributes
Escaped Mode Addressing
Using Escaped Mode Addressing, address modes R or IR specify a Working Register. If
the high nibble of the source or destination address is
EH
(1110B), a Working Register is
inferred. For example, if Working Register R12 (
CH
) is the desired destination operand,
use ECH as the destination operand in the opcode. To access Registers with addresses
E0H
to
EFH
, either set the Working Group Pointer, RP[7:4], to
EH
or use indirect addressing.
C
Unaffected.
Z
Set if the result is zero; reset otherwise.
S
Set if Bit 7 of the result is set; reset otherwise.
V
Reset to 0.
D
Unaffected.
H
Unaffected.
Mnemonic
Destination, Source
Opcode (Hex)
Operand 1
Operand 2
Operand 3
TCM
r1, r2
62
{r1, r2}
—
—
TCM
r1, @r2
63
{r1, r2}
—
—
TCM
R1, R2
64
R2
R1
—
TCM
R1, @R2
65
R2
R1
—
TCM
R1, IM
66
R1
IM
—
TCM
@R1, IM
67
R1
IM
—
