UM012811-0904
eZ8 CPU Instruction Set Summary
eZ8 CPU
User Manual
43
EZ8 CPU INSTRUCTION SUMMARY
Table 20 summarizes the eZ8 CPU instructions. The table identifies the addressing modes
employed by the instruction, the effect upon the Flags register, the number of CPU clock
cycles required for the instruction fetch, and the number of CPU clock cycles required for
the instruction execution.
.
Table 20. eZ8 CPU Instruction Summary
Assembly
Mnemonic
Symbolic Operation
Address Mode
Opcode(s)
(Hex)
Flags
Fetch
Cycles
Instr.
Cycles
dst
src
C
Z
S
V
D
H
ADC dst, src
dst
←
dst + src + C
r
r
12
*
*
*
*
0
*
2
3
r
Ir
13
2
4
R
R
14
3
3
R
IR
15
3
4
R
IM
16
3
3
IR
IM
17
3
4
ADCX dst, src
dst
←
dst + src + C
ER
ER
18
*
*
*
*
0
*
4
3
ER
IM
19
4
3
ADD dst, src
dst
←
dst + src
r
r
02
*
*
*
*
0
*
2
3
r
Ir
03
2
4
R
R
04
3
3
R
IR
05
3
4
R
IM
06
3
3
IR
IM
07
3
4
ADDX dst, src
dst
←
dst + src
ER
ER
08
*
*
*
*
0
*
4
3
ER
IM
09
4
3
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
C = Carry Flag
0 = Reset to 0
1 = Set to 1
