UM012811-0904
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Space
eZ8 CPU
User Manual
15
Figure 3. Register File Organization
Linear Addressing of the Register File
Using 12-bit linear addressing, the eZ8 CPU can directly access any 8-bit registers or 16-
bit register pairs within the 4096B Register File. The instructions that support 12-bit
addressing allow direct register access to most registers without requiring a change to the
value of the Register Pointer (RP). To accommodate the increase in the register address
space relative to the Z8
®
architecture, new Extended Addressing instructions have been
added to allow easier register access across page boundaries.
Page Mode Addressing of the Register File
In Page mode, the Register File is divided into sixteen 256-Byte register Pages. The cur-
rent page is determined by the Page Pointer value, RP[3:0]. Registers can be accessed by
Direct, Indirect, or Indexed Addressing using 8-bit addresses. The full 12-bit address is
given by {RP[3:0], Address[7:0]}. All 256 registers on the current page can be referenced
0
16
256B Pages
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
16
16B Working Register
Groups Per Page
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
000H
FFFH
4096B
Linear Addressable
Register File
16
Working Registers
Per Group
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
